CMOS integrated semiconductor circuit

Details CMOS integrated semiconductor circuit CMOS integrated semiconductor circuit

1995-07-17

1998-04-28

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

327536, H03K 301

Patent

active

057449961

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

The invention relates to an integrated semiconductor circuit employing CMOS technology and to a data processing system, both characterized by low power consumption.


BACKGROUND OF THE INVENTION

Currently available computers, and those anticipated in the near future, suffer from excessive power consumption. The problem is especially great for portable personal computers for which high power consumption is a particular disadvantage under battery operation. Large power consuming components of data processing systems include the display screen, hard disk, internal memory, processor, and other peripheral devices that may be connected. Among the known methods for extending battery life of portable computers is the "standby mode," in which the backlighting of the display screen is turned off after a period of non-use. The display screen is turned on again when the user depresses a key. The hard disk can also be halted in standby mode. Another approach for saving energy is intelligent power management in which components currently not being used are turned off, and therefore consume no power. Energy can also be saved by reducing the clock speed when lower system performance is sufficient. Still another known approach is disconnecting system power, whereby critical information for restart is saved in a special area of the processor ("rest" or "sleep mode"). In the future, systems will also save power by employing processors that operate at a supply voltage of 3.3 volts rather than the current 5 volts.
Another power saving scheme is described in, "Low-Power Data Retention for CCD Memories," by F. J. Aichelmann, Jr., in the IBM Technical Disclosure Bulletin, Vol. 20, No. 11A, April 1978, p. 4415. The article discloses increasing the substrate bias voltage in conjunction with a reduced refresh shift clock frequency to minimize power consumption in a charge coupled device operating on auxiliary power. The substrate bias voltage is increased to the point at which the peripheral support circuits on the CCD still operate at the minimum operating shift frequency. The load current of field effect transistors (FETs), is thereby reduced at constant drain-source voltage, resulting in lower power consumption.
Up to now, none of these approaches has been able to support sufficiently extended battery operation of portable PCs. Further improvement in conserving energy is extremely valuable and is provided by the following invention.


SUMMARY OF THE INVENTION

It is an object of the present invention to provide an integrated semiconductor circuit and a data processing system which, in addition to the currently known approaches, permits further energy saving and thus, even longer battery-based operation.
It is another object of the present invention to provide stable operation of a CMOS integrated circuit at two or more significantly different supply voltages.
It is another object of the present invention to adjust the threshold voltage of each transistor of the CMOS pair so as to provide stable operation at each supply voltage.
These and other objects of the invention are provided by a data processing system comprising an integrated semiconductor circuit including a pair of CMOS transistors, each CMOS transistor of the pair having a threshold voltage that is capable of being adjusted. A higher and a lower clock frequency is available to the integrated semiconductor circuit. A higher and a lower absolute supply voltage level is also available to the integrated semiconductor circuit. The system further comprises means to generate a signal representing the supply voltage level. The system also comprises means to automatically adjust threshold voltages of the CMOS transistors in response to the signal to provide a higher absolute threshold voltage to each CMOS transistor of the pair at the higher level and a lower absolute threshold voltage to each CMOS transistor of the pair at the lower level. The integrated semiconductor circuit is capable of stable operation at the higher clock frequency at the higher abs

REFERENCES:
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patent: 4142114 (1979-02-01), Green
patent: 4705966 (1987-11-01), Van Zanten
patent: 4794278 (1988-12-01), Vajdic
Technical Disclosure, F.J. Aichelmann, Jr., "Low-Power Retention for CCD Memories", vol. 20, No. 11A, Apr. 1978, p. 4415-4416.
Patent Abstracts of Japan, vol. 014, No. 005 (E-869)9. Jan. 1989 & JP, A, 12 53 264 (Sharp Corp)9. Oktober. 1989, siehe Zusammenfassung.
Patent Abstracts of Japan, vol. 015, No. 254 (E-1083)27, Juni 1991 & JP, A, 30 821 151 (Nec Corp)8. Apr. 1991, siehe Zusammenfassung.
Electronics Letters, Bd. 26, Nr. 17, 16. Aug. 1990, Stevenage GB Seiten 1381 -1382, XP000108969, U. Gatti et al. "Automatic switching of substrate bias or well bias in CMOS-IC" *Das ganze Dokument*.
Patent Abstracts of Japan, vol. 013, No. 240 (E-767) 6. Jun. 1989 & JP A, 10 42 850 (NEC Corp) 15. Feb. 1989, siehe Zusammenfassung.

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