CMOS integrated circuit with reduced susceptibility to PMOS punc

Details CMOS integrated circuit with reduced susceptibility to PMOS punc CMOS integrated circuit with reduced susceptibility to PMOS punc

1989-06-27

1990-07-24

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 41, 437 44, 437 56, 437 57, H01L 21265, H01L 2700

Patent

active

049435370

ABSTRACT:
A CMOS integrated circuit, in which the PMOS devices each include a buried channel region (26). The P+ source/drain regions (54) and (56) are separated from the channel region (26) by N-type lateral field isolating regions (58) and (60). Whenever a voltage negative enough to turn on the channel is applied, the isolating regions will be inverted by the electric fields from the corners of the gate. Thus, the value of the transistor's threshold voltage is not changed. However, these lateral field isolating regions provide an electric field modification which helps to minimize drain-induced barrier lowering, and thereby reduces the leakage current of the device in the off state. Preferably the lateral field isolating regions are formed by a doping which is maximal at the same depth (below the gate oxide) at which the threshold-voltage-adjust doping of the channel is maximal.
The preferred CMOS process provides lateral field isolating regions on the PMOS devices, and also provides LDD regions on the NMOS devices. The lateral field isolating regions in the PMOS transistors are formed by a blanket N-type implant, and the LDD regions in the NMOS transistors are formed by a patterned implant. Both of these implanting steps are preferably performed after the polysilicon gate layer is encapsulated (by a thin oxide layer), but before the sidewall oxide spacers (which will define a lateral separation between the gate level and the source/drain implant locations) are formed.

REFERENCES:
patent: Re32800 (1988-12-01), Han et al.
patent: 3305708 (1967-02-01), Ditrick
patent: 3923553 (1975-12-01), Hayashi et al.
patent: 3996655 (1976-12-01), Cunningham et al.
patent: 4062699 (1977-12-01), Armstrong
patent: 4070687 (1978-01-01), Ho et al.
patent: 4078947 (1978-03-01), Johnson et al.
patent: 4142926 (1979-03-01), Morgan
patent: 4143388 (1979-03-01), Esaki et al.
patent: 4173818 (1979-11-01), Bassous et al.
patent: 4205330 (1980-05-01), Klein
patent: 4209349 (1980-06-01), Ho et al.
patent: 4229756 (1980-10-01), Sato et al.
patent: 4236167 (1980-11-01), Woods
patent: 4247860 (1981-01-01), Tihanyi
patent: 4282539 (1981-08-01), Schrader
patent: 4305201 (1981-12-01), Tielert
patent: 4342149 (1982-08-01), Jacobs et al.
patent: 4382826 (1983-05-01), Pfleiderer et al.
patent: 4402761 (1983-09-01), Feist
patent: 4514897 (1985-05-01), Chiu et al.
patent: 4530150 (1985-07-01), Shirato
patent: 4577391 (1986-03-01), Hsia et al.
patent: 4675981 (1987-06-01), Naruke
patent: 4677735 (1987-07-01), Malhi
patent: 4697198 (1987-09-01), Komori
patent: 4703551 (1987-11-01), Szluk et al.
patent: 4746624 (1988-05-01), Cham
patent: 4784968 (1988-11-01), Komori et al.
patent: 4906588 (1990-03-01), Harrington, III
"Self-Aligned P.sup.+ Implanted Regions for Compound Semiconductor FETs", IBM Technical Disclosure Bulletin, vol. 31, No. 4, Sep. 1988, pp 421-423.
Ogura et al., "A Half Micron MOSFET Using Double Implanted LDD", IEDM 1982, pp. 718-721.

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