Patent
1990-07-11
1991-05-14
Wojciechowicz, Edward J.
357 35, 357 48, 357 55, 357 68, 357 86, H01L 2702
Patent
active
050160788
ABSTRACT:
The disclosure concerns integrated circuits and, more particularly, their protection against electrostatic discharges. To protect a metallized pad in a CMOS circuit on an N substrate with P wells, an NPN type lateral bipolar transistor formed in a P-type well is used. The emitter is an N+ region connected to the pad. The collector is an N+ region connected to a metallization which is itself connected, like the substrate N, to the high supply voltage Vcc of the circuit. The well is taken to the potential of the pad to be protected by means of an ohmic contact by a P+ surface diffusion of the well. In the preferred embodiment of the invention, the region that acts as a collector includes a part extending laterally outside the P well, and it is in this external part that the contact with the metallization occurs. The contact is at a sufficient distance from the well for there to be no risk of damage to the trench/substrate junction when the density of current flowing through the metallization is high.
REFERENCES:
patent: 4314267 (1982-02-01), Bergeron et al.
patent: 4419685 (1983-12-01), Sugawara et al.
patent: 4918026 (1990-04-01), Kosiak et al.
Plottel Roland
SGS-Thomson Microelectronics S.A.
Wojciechowicz Edward J.
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