CMOS integrated circuit for signal delay

Details CMOS integrated circuit for signal delay CMOS integrated circuit for signal delay

1986-10-01

1988-05-03

Heyman, John S.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

328 56, 307451, 357 42, H03K 5159, H03K 19094

Patent

active

047422548

ABSTRACT:
A CMOS integrated circuit for signal delay comprises CMOS gate circuits connected in multiple stages which deliver out an input binary signal after delaying it by a predetermined delay time. The CMOS gate circuits are arranged in a folded pattern on an integrated circuit substrate and each row of the folded pattern including a part of the CMOS gate circuits in stages of an odd number. Each of the CMOS gate circuits consists of an N channel element and a P channel element cascade-connected to each other and gate patterns of the respective channels have their width and length adjusted in such a manner that value of operating currents in these elements become equal to each other when the same external voltage has been applied to these elements.

REFERENCES:
patent: 3378783 (1968-04-01), Gibson
patent: 3921101 (1975-11-01), McCoy et al.
patent: 3931588 (1976-01-01), Gehweiler
patent: 4069429 (1978-01-01), White et al.
patent: 4344002 (1982-08-01), Chao
patent: 4504785 (1985-03-01), Tucker et al.
patent: 4504791 (1985-03-01), Conway et al.
RCA COS/MOS Integrated Circuits Manual, 1971 p.24.

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