CMOS integrated circuit failure diagnosis apparatus and diagnost

Details CMOS integrated circuit failure diagnosis apparatus and diagnost CMOS integrated circuit failure diagnosis apparatus and diagnost

1997-01-13

1998-08-04

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

057905657

ABSTRACT:
A failure diagnosis apparatus is provided which predicts failure locations in a CMOS integrated circuit in which an Iddq has been discovered, this apparatus having a test pattern storage unit 1 for storing test patterns used to perform a functional test of the CMOS integrated circuit, an LSI tester 3 which performs a functional test and an Iddq test on the CMOS integrated circuit based on the test patterns, a test results storage unit 6 to store test results, a circuit data storage unit 2 to store various information with regard to the device under test, a logic simulator 5 for receiving the above-noted test patterns and circuit data and performing a logic simulation of the internal operation of the circuit, a simulation results storage unit 7, and a failure location judgment unit 8 for outputting the diagnosis results based on test results and simulation results. This diagnosis apparatus predicts short circuit failures between signal lines and between a signal line and either a power supply line or a ground line, based, on the results of a simulation of internal circuit signal values at a point in time at which a test pattern is applied for which an abnormality is not detected in an Iddq test.

REFERENCES:
European Search Report, dated Jun. 3, 1997.
Chennian Di, et al. "On Accurate Modeling and Efficient Simulation of CMOS Opens", International Test Conference, Paper 40.2, Jan. 1, 1993, pp. 875-882.

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