CMOS Integrated circuit digital crossbar switching arrangement

Details CMOS Integrated circuit digital crossbar switching arrangement CMOS Integrated circuit digital crossbar switching arrangement

1987-06-08

1989-07-18

Yusko, Donald J.

Communications: electrical

Continuously variable indicating

With meter reading

370112, 307243, H04Q 900

Patent

active

048497517

ABSTRACT:
A CMOS logic circuit, such as a crossbar digital switch, multistage multiplexer logic tree in a two-column compact folded layout of two columns, each having a width equal to a single stage of the tree, in order to minimize wiring delays and hence signal skew. Each stage of the tree, except for the first, includes a symmetrized two-input CMOS NAND gate followed in cascade by a symmetrized CMOS INVERTER gate, to minimize signal skew otherwise caused by the difference between pull-up and pull-down gate delays of CMOS gates and the skew otherwise caused by variations in semiconductor manufacturing processing conditions and variations in ambient operating conditions (temperature and power supply voltages). Also, a detailed delay balancing scheme separately for pull-up and pull-down gate delays is implemented along a pair of signal paths for generating each output signal and its simultaneous complement without relative skew between them. In this way a single-chip 64 input.times.17 output CMOS digital crossbar switch can be made to operate with date rates as high as 300 megabits per second.

REFERENCES:
patent: 3184552 (1965-05-01), Macrander
patent: 3551900 (1970-12-01), Annis
patent: 4481623 (1984-12-01), Clark
patent: 4593390 (1986-06-01), Hildebrand et al.
patent: 4698628 (1987-10-01), Herkert et al.
patent: 4716308 (1987-12-01), Matsuo et al.
IEEE Journal of Solid State Circuits, vol. SC-10, No. 2, Apr. 1975, pp. 117-122, "Low Power CML IC Crosspoint Switch Matrix for Space Division Digital Switching Networks", by: Manabu Sunazawa et al.
IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5, Oct. 1986, "Elimination of Process-Dependent Clock Skew in CMOS VLSI", by Masakazu Shoji, pp. 875-880.

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