CMOS Integrated circuit device

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Details

357 59, 357 91, 357 23, H01L 2702, H01L 2978, H01L 2904

Patent

active

044438117

ABSTRACT:
An improved CMOS device and method of making it are provided which utilize basically the standard N-channel self-aligned silicon gate structure and process, modified to include a P-channel transistor. A P-type substrate is used as the starting material, with an N-type tank formed for the P-channel transistor. Field oxide is grown after the N-type tank is formed. A polycrystalline silicon layer is deposited and patterned to create gates for both N- and P-channel transistors, then separately masked P- and N-type diffusions or implants form the sources and drains for the two types of transistors.

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patent: 4244752 (1981-01-01), Henderson et al.
patent: 4325169 (1982-04-01), Ponder et al.
patent: 4327368 (1979-09-01), Uchida

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