CMOS integrated circuit and timing signal generator using same

Details CMOS integrated circuit and timing signal generator using same CMOS integrated circuit and timing signal generator using same

2002-03-05

2003-07-08

Cuneo, Kamand (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S1540PB, C219S209000

Reexamination Certificate

active

06590405

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a CMOS integrated circuit and a timing signal generator using the CMOS integrated circuit, and more particularly, to a CMOS integrated circuit and a timing signal generator using the CMOS integrated circuit to be used in a semiconductor test system for generating timing signals of high timing resolution and accuracy for testing semiconductor devices.
BACKGROUND OF THE INVENTION
In testing semiconductor devices such as ICs and LSIs by a semiconductor test system, such as an IC tester, a semiconductor IC device to be tested is provided with test signals or test patterns produced by a semiconductor test system at its appropriate pins at predetermined test timings. The semiconductor test system receives output signals from the IC device under test in response to the test signals. The output signals are sampled by strobe signals with predetermined timings to be compared with expected data to determine whether the IC device performs intended functions correctly.
To achieve accurate test results, the timings of the test signals and strobe signals must be adjustable with high timing resolution and accuracy. In a semiconductor test system, various timings of the test signals and strobe signals are generated and controlled by a timing generator. Typically, such a timing generator produces various timings (delay times) using signal propagation delay times of CMOS integrated circuits.
An example of configuration in such a timing generator is shown in
FIGS. 4-7
. Typically, such a timing generator is configured in a MOSFET (metal oxide semiconductor filed effect transistor) integrated circuit, especially, a CMOS (complementary MOS) integrated circuit. As shown in
FIG. 4
, an example of timing generator using CMOS integrated circuits is comprised of an electric power source
10
, a control logic block
20
, and a timing generator block
30
. The electric power source
10
is a constant voltage source supplying electric currents to the timing generator block
30
. In this example, a voltage source terminal VDD is connected to the ground (GND) and a voltage source terminal VSS is provided with a negative voltage.
The control logic block
20
is a logic circuit that produces timing data in synchronism with a clock signal for controlling delay times in variable delay circuits
31
in the timing generator block
30
. The timing generator block
30
includes a plurality of variable delay circuits
31
to produce various timings in response to the timing data from the control logic block
20
.
Typically, the timing generator block
30
is formed of a coarse delay circuit and a fine delay circuit such as shown in FIG.
7
. For example, the coarse delay circuit produces a delay time which is an integer multiple of one clock signal period while the fine delay circuit produces a delay time which is a fraction of the one clock signal period. Thus, in this example, the variable delay circuit
31
of
FIG. 4
corresponds to the combination of the coarse delay circuit and the fine delay circuit of FIG.
7
.
The upper part of
FIG. 7
is the coarse delay circuit and the lower part thereof is the fine delay control circuit. In the example of
FIG. 7
, the coarse delay circuit is formed of a counter
71
, a register
72
, a comparator
73
, a flip-flop
74
and an AND gate
76
. In the coarse delay circuit, the counter
71
is reset by a tester rate signal and the coarse delay data in the timing data from the control block
20
is loaded in the register
72
. The counter
71
counts the clock signal. The counted data of the counter
71
is compared with the coarse delay data stored in the register
72
by the comparator
73
.
When both data match with each other, the comparator
73
produces a coincidence signal which is re-timed by the flip-flop
74
and the AND gate
76
. Thus, the output of the AND gate
76
shows a delay time which is an integer multiple of the clock cycle. The delayed output signal from the AND gate
76
is provided with a delay time which is smaller than the clock cycle by the fine delay circuit in the lower part of FIG.
7
.
The fine delay circuit is configured by a plurality of variable delay circuits for producing weighted small delay times. In the example of
FIG. 7
, the fine delay control unit includes a delay unit
77
for generating a delay time equal to a ½ cycle of the clock signal and a delay unit
78
for generating a delay time equal to a ¼ cycle of the clock signal. The delay unit
77
is formed of AND gates
81
and
82
, a delay element
83
, and an OR gate
84
. Similarly, the delay circuit
78
is formed of AND gates
85
and
86
, a delay element
87
, and an OR gate
88
.
The delay elements
83
and
87
respectively produce the above noted delay times which are ½ cycle and ¼ cycle, respectively, of the clock signal. Such delay times are created by combinations of signal propagation delay times of a series connected CMOS transistors or gates forming the delay elements
83
and
87
. In other words, the timing generator of FIG.
4
and the timing generator block of
FIG. 7
are typically formed of a CMOS integrated circuit, the delay elements
83
and
87
in the fine delay circuit operates in an analog fashion while the other parts thereof operate in a digital fashion.
As shown in the circuit configuration of
FIG. 7
, by the fine timing data provided to the AND gates, it is determine as to whether or not the input signal to the delay circuit is introduced to the signal path having the delay element for adding the delay time. As a consequence, at the output of the timing generator block of
FIG. 7
, a timing signal having a high timing resolution is produced. In an actual application to a semiconductor test system, a large number of such delay circuits are employed to produce a fine delay time having timing resolution of, for example, {fraction (1/32)} cycle of the reference clock.
As noted above, each delay element is formed of a CMOS integrated circuit having a large number of CMOS transistors or CMOS gates series connected to one another. Accordingly, the delay time produced by such a delay element tends to be subject to voltage changes or temperature changes, resulting in the timing instability. For example, such temperature changes caused by the environmental changes or the heat dissipated or power consumption by the CMOS integrated circuit itself.
Therefore, in order to obtain the high timing accuracy, it is necessary to remove the factors which cause fluctuations in the transmission delay time in the timing generator block
30
. The temperature variations in the CMOS integrated circuit chip caused by ambient temperature and/or the chip's self-generated heat as well as the source voltage variation account for most of the fluctuations in the delay timings in the timing generator block
30
. The ambient temperature can be stabilized by using an improved cooling means such as a constant temperature chamber or oven. The source voltage can be stabilized by using a high-accuracy voltage regulator that senses the voltage supplied to the CMOS integrated circuit chip and regulate the same to be constant.
However, the temperature changes based on the self-dissipated heat by the CMOS integrated circuit is not easily removable. In a CMOS integrated circuit, electric current flows in an impulse manner during the transition period of each CMOS gate or transistor. In a steady state, after changing the states in the complementary MOS transistors, almost no electric current flows therein. Such transitions occur when a pulse signal propagating through the CMOS integrated circuit. Therefore, power consumption or heat dissipated by the CMOS integrated circuit is a function of the frequency or repetition rate of the pulse signal applied to the CMOS integrated circuit.
FIG. 5
shows the relationship between the signal repetition rate (frequency) in the CMOS integrated circuit and the heat dissipated (power consumed) by the CMOS integrated circuit. The repetition rate is the number of changes in the

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