CMOS input voltage clamp

Details CMOS input voltage clamp CMOS input voltage clamp

1994-10-03

1996-06-18

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

327318, 327323, 326 30, H03K 508, H03K 1716

Patent

active

055281907

ABSTRACT:
A voltage clamping circuit is provided for clamping the input voltage to CMOS devices near the rail voltages so as to prevent forward biased junctions, minority carrier injection and crosstalk between voltage inputs. The voltage clamping circuit receives an input voltage and provides an output voltage within a rail-to-rail voltage range. The clamping circuit has a bias circuit with a PMOS device for providing a p-channel threshold drop to an upper rail voltage so as to generate an upper threshold bias voltage. The bias circuit also has an NMOS device for providing an n-channel threshold increase to a lower rail voltage so as to generate a lower threshold bias voltage. A first clamping transistor is coupled to the input for clamping the input voltage so as to prevent the input voltage from rising above the upper rail voltage. A second clamping transistor is coupled to the input for clamping the input voltage so as to prevent the input voltage from dropping below the lower rail voltage. Gain stages control the clamping transistors in response to the upper and lower threshold bias voltages and the input voltage so as to cause the clamping transistors to clamp the input voltage.

REFERENCES:
patent: 4590394 (1986-05-01), Pace
patent: 4874967 (1989-10-01), Deane
patent: 4908528 (1990-03-01), Huang
patent: 4958093 (1990-09-01), Kosson et al.
patent: 5021747 (1991-06-01), Isham et al.
patent: 5027008 (1991-06-01), Runaldue
patent: 5159216 (1992-10-01), Taylor et al.
patent: 5206544 (1993-04-01), Chen et al.

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