CMOS input buffer with switched capacitor reference voltage gene

Details CMOS input buffer with switched capacitor reference voltage gene CMOS input buffer with switched capacitor reference voltage gene

1988-06-16

1989-07-18

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307350, 307362, 307310, 307264, 3072968, 323281, H03K 19092, H03L 500

Patent

active

048496618

ABSTRACT:
An input buffer circuit for providing corresponding CMOS compatible signals to an input signal. The input buffer circuit is comprised of a switched-capacitor voltage division network for providing a reference voltage to a comparator. The comparator accepts an input voltage and determines if the input voltage is greater or less than the reference voltage and generates a CMOS compatible output, which is determined by the value of the input signal in reference to the reference voltage. The reference voltage generator is comprised of two capacitive devices, wherein the first capacitive device is charged and the second capacitive device is discharged during a first time period and the charges on the two capacitive devices are shared during a second time period. A ratio of the capacitances of these two capacitive devices determines the voltage value at the junction of the two capacitors, which then determines the reference voltage. The two capacitors are comprised of an n-type device and a p-type device to provide immunity to variations in process and temperature.

REFERENCES:
patent: 4433282 (1984-02-01), Squires
patent: 4488229 (1984-12-01), Harrison
patent: 4574250 (1986-03-01), Senderowicz
patent: 4633223 (1986-12-01), Senderowicz
patent: 4677321 (1987-06-01), Bacrania
patent: 4698527 (1987-10-01), Matsumoto

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