CMOS input buffer with low power consumption

Details CMOS input buffer with low power consumption CMOS input buffer with low power consumption

1991-03-25

1992-09-29

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307246, 307451, H03K 1716

Patent

active

051516209

ABSTRACT:
A buffer circuit for connecting a CMOS logic circuit to receive TTL logic level signals assures that the upper and lower FET's of an otherwise conventional input inverter stage do not both turn on together in the situation in which an input signal has a level that is high enough to turn on the lower FET but not high enough to turn off the upper FET. A third and a fourth FET are connected to form a controlled power supply stage that controls the current supplied to the upper FET. The third FET has its gate connected to be controlled from the output of a second inverter stage (which is in phase with the input to the first stage). When the TTL input rises, the second inverter stage output turns off the third FET and thereby turns off the upper FET. The fourth FET is connected as a capacitor that is charged while the third FET is turned on and then supplies current to switch the output inverter stage when the upper FET is turned on. A fifth FET is connected to charge the capacitor and a circuit is provided to detect when power is initially supplied to the buffer circuit and to turn on the fifth FET momentarily to initially charge the capacitor.

REFERENCES:
patent: 4258272 (1981-03-01), Huang
patent: 4437024 (1984-03-01), Wacyk
patent: 4818901 (1989-04-01), Young et al.
patent: 4825106 (1989-04-01), Tipon et al.
patent: 4929853 (1990-05-01), Kim et al.
patent: 4973861 (1990-11-01), Dikken
patent: 5034623 (1991-07-01), McAdams

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