CMOS input buffer with high speed and low power

Details CMOS input buffer with high speed and low power CMOS input buffer with high speed and low power

1991-12-12

1994-04-19

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307548, H03K 1716

Patent

active

053048679

ABSTRACT:
Prior-art high speed TTL-to-CMOS input buffers consume a large amount of power supply current through the input transistors when the input voltage is held at a mid-range level between V.sub.DD and V.sub.SS (e.g., 2.0 volts). The inventive input buffer includes a resistance in series with the p-channel pull-up transistor on the input inverter, in order to limit this current. In addition, to retain high operating speed, a p-channel shunt transistor is placed in parallel with the resistance, and controlled by the buffer output signal. This shunt transistor effectively bypasses the resistance from the circuit when the buffer output goes low, thereby providing high operating speed.

REFERENCES:
patent: 4210829 (1980-07-01), Wong et al.
patent: 4437024 (1984-03-01), Wacyk
patent: 4471242 (1984-09-01), Noufer et al.
patent: 4672243 (1987-06-01), Krisch
patent: 4791323 (1988-12-01), Austin
patent: 4806801 (1989-02-01), Argade
patent: 4825106 (1989-04-01), Tipon et al.
patent: 5036226 (1991-07-01), Tonnu et al.
patent: 5144167 (1992-09-01), McClintock
patent: 5151622 (1992-09-01), Thrower

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