CMOS input buffer accepting TTL level inputs

Details CMOS input buffer accepting TTL level inputs CMOS input buffer accepting TTL level inputs

1985-09-03

1987-02-10

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307360, 307297, H03K 19094

Patent

active

046424881

ABSTRACT:
A Complementary Metal Oxide Semiconductor (CMOS) input buffer circuit is provided which accepts Transistor-Transistor Lock (TTL) input signal levels without generating any significant DC current path. A reference voltage circuit (1, FIG. 1) provides first and second reference voltages (V.sub.A and V.sub.B, FIG. 1) which are coupled to first and second stages, respectively, of the input buffer circuit (3, FIG. 1), and which are of predetermined magnitudes and scaled relative to each other to permit the P-channel devices of the input buffer circuit to turn off completely when the input to the circuit is "high", while allowing a successively higher output at each successive stage of the input buffer circuit. The reference circuit 1 is compensated for power supply and process window variations.

REFERENCES:
patent: 4242604 (1980-12-01), Smith
patent: 4471242 (1984-09-01), Noufer et al.
patent: 4472647 (1984-09-01), Allgood et al.
patent: 4477737 (1984-10-01), Ulmer et al.
patent: 4482824 (1984-11-01), Tzeng
patent: 4501978 (1985-02-01), Gentile et al.
patent: 4521696 (1985-04-01), Raghunathan
patent: 4555642 (1985-11-01), Morales
patent: 4585955 (1986-04-01), Uchida

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