CMOS imager with improved sensitivity

Active solid-state devices (e.g. – transistors – solid-state diode – Responsive to non-electrical signal – Electromagnetic or particle radiation

Utility Patent

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Details

C257S282000, C257S369000, C257S431000, C257S444000

Utility Patent

active

06169318

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an improved pixel design for a CMOS imager. More particularly, the invention relates to a pixel design which maintains a high quantum efficiency in spite of a shrinking feature size thereby providing highly sensitive sensors with a high pixel density. The novel pixel design can also incorporate anti-blooming protection.
2. Description of Related Art
Solid-state image sensors, such as CCD and CMOS based image sensors, are commonly used as input devices for electronic video and still cameras, machine vision, etc. The sensors are comprised of pixels arranged in rows and columns, for example in 512 rows and 768 columns for a total of approximately 400,000 pixels in an image sensor with a moderate resolution. The spatial resolution of an electronic imaging device is limited by the number of pixels; high resolution image sensors for generating prints with a quality approaching that of photographic pictures recorded on conventional color film require in excess of 1 million pixels per imager. As a result, the lateral dimensions and feature size of the individual pixels in high resolution image sensors decrease with increasing number of pixels per unit area. As the feature size in advanced CMOS processes shrinks, the doping levels and layer thicknesses have to be scaled accordingly and additional process steps are added to enhance circuit performance. On the other hand, the optically active volume from which photo-generated charge can be collected, has to remain large enough for collecting a sufficient amount of radiation energy at the wavelength of interest, in particular at wavelengths between about 300 nm and about 800 nm, i.e. in the UV-IR spectral range. Because the absorption constant for optical radiation in semiconductors generally decreases with increasing wavelength, i.e. the red-IR portion of the light is penetrates the semiconductor to a greater depth than the blueUV portion of the light, the red-IR portion generates electric charges farther away from the semiconductor surface or the p-n junction of the photo element, respectively. The spectral response of a Si p-n junction solar cell which has substantially the same structure as the photo element of a CMOS image sensor, is discussed, for example, in S. M. Sze,
Physics of Semiconductor Devices
, John Wiley & Sons (1981), p. 800-805.
A simple CMOS technology employs two basic types of FET's, namely n-MOS FET's and p-MOS FET's. Most CMOS processes start with a p-doped substrate or with a p-type epitaxial layer deposited by known methods on a substrate of a different doping-type, such as an insulating or n-type substrate, with the substrates predominantly made of silicon. The p-dopant level of the substrate is typically around 1×10
15
cm
−3
. Other substrates, for example sapphire, can also serve as carriers for the p-type epitaxial layer. Both the p-doped substrate and the p-type epitaxial layer with hereinafter be referred to as p-substrate. N-MOS FET's are built in the uniformly doped p-type substrate through patterning of an active window with a gate oxide having an active gate disposed thereon, wherein the active area not covered by the gate is subsequently doped n
+
-type by known methods to a level of typically 1×10
19
to 1×10
21
cm
−3
. P-MOS FET's are built in an n-type well formed in the p-doped substrate through patterning of an active window with a gate oxide having an active gate disposed thereon, wherein the active area not covered by the gate is subsequently doped p-type.
The photo element of CMOS image sensor pixels is typically a simple diode in the form of an n
+
-well formed in the p-type substrate; if the source or drain region of an n-MOS FET transistor is to be electrically connected to the n
+
-well of the photo element, then the n
+
-doping region can be contiguous between these two devices. An n-MOS FET of this type is used, for example, to first set the n
+
-doping region to a positive voltage and then to isolate the n
+
-doping region for integrating the charges generated by the impinging radiation. The pixel preferably includes additional FET's for buffering the generated charge as well as for selectively connecting the photo element and/or a sense node to a bias for reset and to a circuit for readout. The FET's are connected row-wise and column-wise to row-select and row-rest lines for selecting and resetting the pixels and to column-wise signal lines for reading out the photo-generated signals in a manner known in the art.
As the feature size in advanced CMOS processes shrinks, the doping levels and layer thicknesses are scaled accordingly, and additional process steps known in the art are added to enhance device performance. More particularly, n-MOS FET's with small gate length require a higher p-doping level in the gate channel; in a typical process, the n-MOS FET's are formed by first forming in the substrate a p-well with a higher p-doping level than the substrate extending area-wise across the entire source-gate-drain region. The source and drain regions are subsequently formed by n
+
-doping the p-well. In the typical CMOS process adapted to small feature sizes, the photo element is usually also formed in such higher p-doped well instead of directly in the substrate. This is disadvantageous for the reasons described below.
As mentioned before, the photo element collects the electric charges (electrons in the n
+
-region and holes in the p-well and/or substrate) generated by the optical radiation impinging on the CMOS image sensor. Charge collection begins when the photo element is isolated from a reference voltage V
REF
by removing the gate voltage from the row reset FET; the electrons or holes then drift or diffuse until they cross the space-charge region near the p-n
+
interface, causing the reverse bias across the photo element to decrease. However, with shrinking feature size, as described before, the doping levels, especially that of the p-doped active area of the FET'S, are preferably increased above the doping level of the p-doped substrate to control the electrical device parameters. This higher doped p-layer creates a diffusion barrier for the electrons which are generated at a greater depth inside the p-doped substrate or epilayer, which can prevent these electrons from reaching the n
+
-doping region. Consequently, the quantum efficiency of the CMOS image sensor is decreased, in particular in the red-IR spectral range, as discussed above. Moreover, these electrons may also drift laterally to adjacent pixels and thus impair the spatial resolution and induce blooming at higher incident radiation intensity.
SUMMARY OF THE INVENTION
With the foregoing in mind, it is therefore an object of the invention to provide an improved CMOS image sensor with an efficient charge collection efficiency, in particular at high pixel densities and small feature sizes. It is another object of the invention to provide a CMOS image sensor wherein the spectral response to the wavelength of the incident optical radiation is not adversely affected by the doping levels required for the peripheral devices, such as the FET's integrated with the pixel.
It is still another object of the invention to reduce blooming effects at high incident radiation levels.
These objects are solved by the invention by forming only the n-MOS FET's in p-wells with an increased p-doping concentration and forming the photo element itself in the lower p-doped substrate.
In another advantageous embodiment, the p-doping concentration is increased only in the FET channel, but not underneath the source and drain regions of the FET's. In yet another advantageous embodiment, the higher p-doped regions extend along the periphery of the photo element and possibly also along the periphery of at least some of the source and drain regions of the FET's.


REFERENCES:
patent: 3680484 (1972-08-01), Stetter
patent:

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