CMOS imager with discharge path to suppress reset noise

Details CMOS imager with discharge path to suppress reset noise CMOS imager with discharge path to suppress reset noise

2000-10-05

2003-09-09

Kim, Robert H. (Department: 2882)

Radiant energy

Photocells; circuits and apparatus

Photocell controlled circuit

C250S2140RC, C257S290000, C257S291000

Reexamination Certificate

active

06617562

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates generally to electronic imaging devices and, in particular, to an electronic imaging device that suppresses reset noise in an image sensor.
2. Related Art
Photosensor image processing in camera and video systems commonly utilize CMOS image sensors that have cost and power advantages over other technologies such as charge coupled devices (CCD). A conventional CMOS image sensor has a photo-detector that is reset to a known potential after the readout of each image by a NMOS FET acting as a reset switch. When the NMOS FET reset switch is “switched off,” charge left in the NMOS FET channel drifts back to the photo-detector and produces reset noise. A common measure of reset noise is the product of the Boltzman's constant “k”, temperature “T”, and capacitance “C” (typically known as kTC) and represents an uncertainty about the voltage on the photo-detector following a reset.
CMOS imager sensors typically utilize off-chip signal processing to improve signal to noise (S/N) performance and compensate for the reset noise generated by a conventional NMOS FET acting as a reset switch. In addition, utilization of a conventional NMOS FET as a reset switch adds a significantly large capacitance component to the photodiode because of the FET's moderately doped p-well being in direct contact with the more heavily doped drain implant. This increased capacitance results in a loss of sensitivity in the CMOS image sensors.
Additionally, the sub-micron fabrication technology utilized in conventional NMOS FET fabrication is not optimized to reduce junction leakage. Junction leakage in a MOS FET results from an increased electric field associated with a shallow junction, Arsenic implant damage, and gate induced drain leakage. Furthermore, when the gate threshold is too low, which is the typical case for the conventional sub-micron NMOS FET, continuous soft resets results due to sub-threshold leakage. Junction leakage associated with poor junction optimization and continuous soft resets in a CMOS image sensor contribute to reset noise and a loss of sensitivity at low light levels. What is needed in the art is an approach to reduce reset noise, typically the dominant source of noise, in CMOS imager sensor without reducing the area available for light collection.
SUMMARY
A CMOS imager with a discharge path to suppress reset noise is provided. The CMOS imager has a discharge path and a reset contact electrically connected to the photo-detector. The discharge path may enable charge flow between the reset contact and the photo-detector. The CMOS image sensor suppresses reset noise by utilizing an image sensor that has a discharge path, rather than utilizing a conventional CMOS device, such as a NMOS FET, as a reset switch.
The reset of a photo-detector to a known potential is achieved by applying a high reverse bias to a reset node that is in close proximity to the photodiode junction. The reset node junction and the photodiode junction are of the same polarity. As the bias is increased, the depletion regions of the reset junction and the photodiode junction merge to establish a common potential. The potential on the reset junction is removed and the depletion regions separate at the end of the reset leaving the photodiode in isolation as a reverse biased junction with a fixed potential. In this manner, the kTC noise associated with the reset through a NMOS FET reset switch is eliminated.


REFERENCES:
patent: 5981932 (1999-11-01), Guerrieri et al.
patent: 6271553 (2001-08-01), Pan

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