CMOS imager with an A/D per pixel convertor

Details CMOS imager with an A/D per pixel convertor CMOS imager with an A/D per pixel convertor

1999-04-15

2001-08-07

Jeanpierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000

Reexamination Certificate

active

06271785

ABSTRACT:

TECHNICAL FIELD
The present invention relates in general to an image signal processing system and more specifically to an image sensor circuit and related method of converting image signals from their analog to digital equivalent by placing a comparator circuit at each pixel in the image sensor array.
BACKGROUND OF THE INVENTION
Solid state imaging systems have been in use for a number of years in high-tech devices such as medical instruments, satellites and telescopes. More recently, imagers have been employed in a wide array of mainstream applications such as digital cameras, camcorders and scanners. Most of these applications use Charge-Coupled Devices (“CCD”) to build the underlying solid state image sensors.
For various reasons, CCD-based image sensors are limited or impractical for use in many consumer applications. First, CCDs require at least two polysilicon layers with a buried-channel implant to-achieve their high performance, meaning that they cannot be fabricated using standard CMOS fabrication processes. Second, the level of integration that can be achieved with CCD-based imagers is low since they can not include the devices necessary to integrate them with other devices in the application. Finally, the circuits used to transfer data out of the image array to other devices on the system board, such as Digital Signal Processors (“DSPs”) and other image processing circuits, have a large capacitance and require voltages higher than the other circuits. Since the currents associated with charging and discharging these capacitors are usually significant, a CCD imager is not particularly well suited for portable or battery operated applications.
As such, less expensive image sensors fabricated out of an integrated circuits using standard CMOS processes are desirable. Essentially, with a CMOS type imager sensor, a photo diode, photo transistor or other similar device is employed as a light detecting element. The output of the light detecting element is an analog signal whose magnitude is approximately proportional to the amount of light received by the element. CMOS imagers are preferred in some applications since they use less power, have lower fabrication costs and offer higher system integration compared to imagers made with CCD processes. Moreover, CMOS imagers have the added advantages that they can be manufactured using processes similar to those commonly used to manufacture logic transistors.
An important signal processing circuit is the analog to digital convertor (“ADC”). In the last few years, CMOS imagers have been developed with the ADC on the imager itself. The optimal place for the ADC is immediately after the photosensor, i.e., on the pixel itself. An example of a prior CMOS image sensor is described in the article entitled “A 128 by 128 Pixel CMOS Area Image Sensor With Multiplex Pixel Line A/D Conversion”, IEEE 1996 Custom Integrated Circuits Conference, Yang, David X. D., Fowler, Boyd, Gamal, EL Abbas. In their article, the authors describe an image sensor consisting of an array of pixel blocks wherein each block further consists of a group of four nearest neighbor pixels sharing a single Analog to Digital (“A/D”) convertor.
A limitation inherent to such sensors is the use of over-sampling A/D conversion methods which require a clock rate well above the image frame rate. The need to keep the conversion rate high in such image sensors requires a substantial amount of drive current making the sensor impractical for many mainstream applications including battery powered or portable devices.
Another problem common to prior art CMOS image sensors is the amount of fixed pattern noise due to beta variations from pixel to pixel which can often be seen with the naked eye. Other undesirable features of prior art CMOS image sensors include large comparator offsets, high complexity of the A/D conversion circuitry, high power dissipation and the inability to achieve a non-linear response for certain applications.
SUMMARY OF THE INVENTION
In accordance with the present invention, the disadvatages and problems associated with the prior CMOS image sensors are substantially reduced or eliminated.
According to one embodiment, disclosed is an image sensor which can be fabricated using a conventional CMOS process. A comparator circuit is placed at each pixel having a first input connected to a photodiode, photo transistor or other similar light detecting element, and a second input connected to a ramp signal generator. Since the comparator circuits are relatively simple devices, they are small enough to be fabricated within individual pixel cells and are effective at eliminating the noise associated with prior art conversion techniques.
In one embodiment, the ramp signal generator comprises a Digital to Analog Conversion “DAC” circuit that drives one input of the comparator circuit. A counter can be coupled to the digital side of the DAC circuit and configured to count from 2
N−1
to 0, N representing the resolution of the light detecting element.
In one embodiment, the pixels are arranged in a two-dimensional array of columns and rows. For each row of pixels, the counter drives the DAC circuit which, in turn, outputs an analog signal proportional to the value received from the counter. A converter and register are connected so that the output of the counter drive the register, and the load signal of the register is connected to the output of the comparator circuit. The output of the DAC circuit is fed to the comparator circuit which flips when the ramp signal equals the value of the light detecting element. The counter value loaded into the register at the time the comparator flips is the digital representation of the analog output of the light detecting element.
In another embodiment, the ramp signal can be generated by other means, such as a capacitor fed by a constant current source, the output of the capacitor being followed by a unity gain voltage buffer whose output is the ramp signal.
In another embodiment, when a nonlinear response is desired, a programmable memory means such as ROM, EEPROM, or RAM may be employed to store values corresponding to the desired response curve. The values may be loaded into the DAC circuit and converterd as herein described to obtain a non-linear response.
According to another embodiment, each comparator circuit is reset to eliminate variations in comparator offsets by resetting the pixels to their settling or zero light value prior to the analog digital conversion sequence.
According to another embodiment, a single D/A conversion circuit is associated with the entire pixel array which may consist of N by M pixels. The D/A conversion circuit drives only a single row at a time with the corresponding comparator circuit in that row driving the associated register loads at one time.
Other advantages of the present invention, including specific implementations, are understood by reference to the following detailed description taken in conjunction with the appended drawings.


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Ludwig, David E., et al.;On-Focal Plane Analog-to-Digital Conversion With Detector Gain and Offset Compensation,Proc. Of SPIE, vol. 1097, Materials, Devices, Techniques, and Applications for Z-Plane Focal Plane Array (FPA) Technology, Mar. 29, 1989, Bellingham, VA, pp. 73-84, Fig. 6.

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