CMOS imager with a self-aligned buried contact

Details CMOS imager with a self-aligned buried contact CMOS imager with a self-aligned buried contact

2002-10-24

2004-07-27

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Forming schottky junction

Compound semiconductor

C438S197000

Reexamination Certificate

active

06767811

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to improved semiconductor imaging devices and in particular to a silicon imaging device which can be fabricated using a standard CMOS process. Particularly, the invention relates to CMOS imager having a self-aligned buried contact formed between a pair of transistor gates or a transistor gate and an isolation region.
DISCUSSION OF RELATED ART
There are a number of different types of semiconductor-based imagers, including charge coupled devices (CCDs), photodiode arrays, charge injection devices and hybrid focal plane arrays. CCDs are often employed for image acquisition and enjoy a number of advantages which makes it the incumbent technology, particularly for small size imaging applications. CCDs are also capable of large formats with small pixel size and they employ low noise charge domain processing techniques. However, CCD imagers also suffer from a number of disadvantages. For example, they are susceptible to radiation damage, they exhibit destructive read out over time, they require good light shielding to avoid image smear and they have a high power dissipation for large arrays. Additionally, while offering high performance, CCD arrays are difficult to integrate with CMOS processing in part due to a different processing technology and to their high capacitances, complicating the integration of on-chip drive and signal processing electronics with the CCD array. While there has been some attempts to integrate on-chip signal processing with the CCD array, these attempts have not been entirely successful. CCDs also must transfer an image by line charge transfers from pixel to pixel, requiring that the entire array be read out into a memory before individual pixels or groups of pixels can be accessed and processed. This takes time. CCDs may also suffer from incomplete charge transfer from pixel to pixel during charge transfer which also results in image smear.
Because of the inherent limitations in CCD technology, there is an interest in CMOS imagers for possible use as low cost imaging devices. A fully compatible CMOS sensor technology enabling a higher level of integration of an image array with associated processing circuits would be beneficial to many digital applications such as, for example, in cameras, scanners, machine vision systems, vehicle navigation systems, video telephones, computer input devices, surveillance systems, auto focus systems, star trackers, motion detection systems, image stabilization systems and data compression systems for high-definition television.
The advantages of CMOS imagers over CCD imagers are that CMOS imagers have a low voltage operation and low power consumption; CMOS imagers are compatible with integrated on-chip electronics (control logic and timing, image processing, and signal conditioning such as A/D conversion); CMOS imagers allow random access to the image data; and CMOS imagers have lower fabrication costs as compared with the conventional CCD since standard CMOS processing techniques can be used. Additionally, low power consumption is achieved for CMOS imagers because only one row of pixels at a time needs to be active during the readout and there is no charge transfer (and associated switching) from pixel to pixel during image acquisition. On-chip integration of electronics is particularly advantageous because of the potential to perform many signal conditioning functions in the digital domain (versus analog signal processing) as well as to achieve a reduction in system size and cost.
A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including either a photogate, a photodiode, or a photoconductor overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. A readout circuit is connected to each pixel cell and includes at least an output field effect transistor formed in the substrate and a charge transfer section formed on the substrate adjacent the photogate, photodiode, or the photoconductor having a sensing node, typically a floating diffusion node, connected to the gate of an output transistor. The imager may include at least one electronic device such as a transistor for transferring charge from the underlying portion of the substrate to the floating diffusion node and one device, also typically a transistor, for resetting the node to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to the floating diffusion node accompanied by charge amplification; (4) resetting the floating diffusion node to a known state before the transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the floating diffusion node. The charge at the floating diffusion node is typically converted to a pixel output voltage by a source follower output transistor. The photosensitive element of a CMOS imager pixel is typically either a depleted p-n junction photodiode or a field induced depletion region beneath a photogate or a photoconductor. For photodiodes, image lag can be eliminated by completely depleting the photodiode upon readout.
CMOS imagers of the type discussed above are generally known as discussed, for example, in Nixon et al., “256×256 CMOS Active Pixel Sensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol. 31(12) pp. 2046-2050, 1996; Mendis et al, “CMOS Active Pixel Image Sensors,” IEEE Transactions on Electron Devices, Vol. 41(3) pp. 452-453, 1994 as well as U.S. Pat. No. 5,708,263 and U.S. Pat. No. 5,471,515, which are herein incorporated by reference.
To provide context for the invention, an exemplary CMOS imaging circuit is described below with reference to FIG.
1
. The circuit described below, for example, includes a photogate for accumulating photo-generated charge in an underlying portion of the substrate. It should be understood that the CMOS imager may include a photodiode or other image to charge converting device, in lieu of a photogate, as the initial accumulator for photo-generated charge.
Reference is now made to
FIG. 1
which shows a simplified circuit for a pixel of an exemplary CMOS imager using a photogate and having a pixel photodetector circuit
14
and a readout circuit
60
. It should be understood that while
FIG. 1
shows the circuitry for operation of a single pixel, that in practical use there will be an M×N array of pixels arranged in rows and columns with the pixels of the array accessed using row and column select circuitry, as described in more detail below.
The photodetector circuit
14
is shown in part as a cross-sectional view of a semiconductor substrate
16
typically a p-type silicon, having a surface well of p-type material
20
. An optional layer
18
of p-type material may be used if desired, but is not required. Substrate
16
may be formed of, for example, Si, SiGe, Ge, and GaAs. Typically the entire substrate
16
is p-type doped silicon substrate and may contain a surface p-well
20
(with layer
18
omitted), but many other options are possible, such as, for example p on p− substrates, p on p+ substrates, p-wells in n-type substrates or the like. The terms wafer or substrate used in the description includes any semiconductor-based structure having an exposed surface in which to form the circuit structure used in the invention. Wafer and substrate are to be understood as including, silicon-on-insulator (SOI) technology, silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the ba

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