CMOS image sensor with substrate noise barrier

Details CMOS image sensor with substrate noise barrier CMOS image sensor with substrate noise barrier

2005-02-08

2005-02-08

Brewster, William M. (Department: 2823)

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

Responsive to electromagnetic radiation

C438S075000, C438S076000, C438S200000

Reexamination Certificate

active

06852565

ABSTRACT:
An image sensor element includes a vertical overflow drain structure to eliminate substrate charge diffusion causing CMOS image sensor noise. An extra chemical mechanical polish step used to shorten the micro-lens to silicon surface distance in order to reduce optical cross talking. One embodiment uses N type substrate material with P− epitaxial layer to form a vertical overflow drain. Deep P well implantation is introduced to the standard CMOS process to prevent latch-up between an N well to an N type substrate. A photo diode is realized by stacked N well/Deep N well and stacked P well/Deep P well to improve performance.

REFERENCES:
patent: 6084259 (2000-07-01), Kwon et al.
patent: 6472698 (2002-10-01), Nakashiba
patent: 6586789 (2003-07-01), Zhao
patent: 20020100915 (2002-08-01), Hynecek
patent: 2240429 (1991-07-01), None

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