CMOS image sensor with reduced fixed pattern noise

Details CMOS image sensor with reduced fixed pattern noise CMOS image sensor with reduced fixed pattern noise

1997-06-02

2001-11-20

Garber, Wendy R. (Department: 2612)

Television

Camera, system and detail

Combined image signal generator and general image signal...

C250S208100, C348S310000, C348S312000

Reexamination Certificate

active

06320616

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to imaging devices and, in particular, to complementary metal-oxide semiconductor (CMOS) image sensors with reduced fixed pattern noise.
2. Description of the Related Art
Various types of imagers or image sensors are in use today, including charge-coupled device (CCD) image sensors and complementary metal-oxide semiconductor CMOS image sensors. CMOS image sensors typically utilize an array of active pixel image sensors and a row or register of correlated double-sampling (CDS) circuits or amplifiers to sample and hold the output of a given row of pixel image sensors of the array. Each active pixel image sensor of the array of pixels typically contains a pixel amplifying device (usually a source follower). The term active pixel sensor (APS) refers to electronic image sensors within active devices, such as transistors, that are associated with each pixel. CMOS image sensors are often interchangeably referred to as CMOS APS imagers or as CMOS active pixel image sensors. The active pixel image sensors and accompanying circuitry for each pixel of the array will be referred to herein as APS circuits.
CMOS image sensors have several advantages over CCD image sensors. For example, CCD image sensors are not easily integrated with CMOS process peripheral circuitry due to complex fabrication requirements and relatively high cost. However, since CMOS image sensors are formed with the same CMOS process technology as the peripheral circuitry required to operate the CMOS image sensor, such sensors easier to integrate into a single system-on-chip using integrated circuit (IC) fabrication processes. By using CMOS image sensors, it is possible to have monolithic integration of control logic and timing, image processing, and signal-processing circuitry such as analog-to-digital (A/D) conversion, all within a single sensor chip. Thus, CMOS image sensors can be manufactured at low cost, relative to CCD image sensors, using standard CMOS IC fabrication processes.
Additionally, CCD image sensors typically require three different input voltages with separate power supplies to drive them. CCD images sensors also require relatively high power supply voltages and thus also require relatively high power to operate. By contrast, CMOS devices require only a single power supply, which may also be used to drive peripheral circuitry. This gives CMOS image sensors an advantage in terms of power consumption, and also in terms of the amount of chip area or “real-estate” devoted to power supplies. CMOS image sensors have relatively low power requirements because of the relatively low voltage power supply required for operation, and also because only one row of pixels in the APS array needs to be active during readout.
Despite these advantages, however, CMOS image sensors also have various disadvantages in comparison to CCD image sensors. For example, in conventional CMOS image sensor architecture, a selected or active row of APS pixel circuits is read out in parallel to the row of CDS circuits during a horizontal blanking period. The output of the row of CDS circuits is then scanned rapidly by a horizontal shift register to read the line out to a common output port. One problem with this approach is that any mismatch between the CDS circuits results in a column fixed pattern noise (FPN) artifact in the captured image. Such mismatches are typically caused by different dc and gain offsets in the signal amplification and processing provided by the CDS circuits. FPN artifacts produced by CMOS image sensors are typically very visible since they are not randomly distributed across the image, but are lined up on a column-by-column basis. CCD devices are usually less prone to FPN artifacts since the actual signal charges captured are transferred to and stored in a serial CCD register, and are thus not as affected by differences in signal gain and offset from column to column.
Current CMOS image sensors, therefore, still have inferior imaging performance compared to CCD imagers, due to excessive FPN, and also due to limited dynamic range (about 72 dB) (which is reduced, in part, by excessive FPN), and low fill factor (the ratio of photodetector area to total area of the APS pixel circuitry) which results in lower sensitivity. There is, therefore, a need for improved CMOS image sensors.
SUMMARY
A correlated double-sampling circuit for sampling an input signal received from a pixel sensor circuit via an input line. According to one embodiment, a first switch selectively couples a junction of first terminals of a first capacitor and a second capacitor to the input line. A second switch selectively couples an output node coupled to a second terminal of the second capacitor to a reference voltage. A third switch selectively couples the output node to an output line.


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