Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Reexamination Certificate
2002-01-10
2003-06-17
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
C257S229000, C257S230000, C257S234000, C257S236000, C257S238000, C257S242000
Reexamination Certificate
active
06580106
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to solid-state image sensors, specifically to Active Pixel CMOS Image Sensors (APS) employing pixels that can be readout repeatedly and do not generate kTC noise.
BACKGROUND OF THE INVENTION
A typical image sensor senses light by converting impinging photons into electrons that are integrated (collected) in sensor pixels. After the integration cycle is completed, charge is converted into a voltage that is supplied to the output terminals of the sensor. An example of the pixel circuit diagram
101
for a typical active pixel CMOS image sensor array
100
is shown in FIG.
1
. In this example, the charge to voltage conversion is accomplished by directly integrating charge on the pixel capacitor represented here by the reverse biased diode
102
. Charge can be also integrated elsewhere in the pixel, for example in a pinned photodiode (U.S. Pat. No. 6,023,081 to Drowley), and transferred on the pixel capacitor later at a suitable time. The charge conversion capacitor is typically connected to the gate of MOS transistor
103
whose source is further connected through the addressing transistor
104
to the array column sense line
105
. The column sense line is shared with other pixels of the same column. The change of source voltage of transistor
103
, induced by collected charge, is thus transferred to the column sense line
105
, and further through the horizontal scanner and buffer circuits
111
of the array to sensor output terminals
112
. Applying pulses to the gates of transistors
104
through horizontal address lines
106
addresses the pixels of the array. The vertical scanner
113
generates the suitable pulses. After charge has been transferred on the capacitor
102
, and read out, it has to be removed. This is accomplished by momentarily turning on the reset transistor
107
by applying reset pulse
108
to its gate. Reset transistor drain
107
is connected to the reference bias
109
. In some cases, the reference bias is identical with the transistor
103
drain bias
110
. A typical prior art CMOS image sensor is described, for example, in U.S. Pat. No. 6,040,592 to McDaniel.
The sensing method described above is known in the art as the destructive charge readout that generates kTC noise. This is caused by equilibrating the node charge fermi level with the fermi level of the reference, which leaves some residual charge on the node. The fluctuations in the amount of residual charge generate kTC noise.
There is a well-known technique, used in the art, to minimize the undesirable effects of kTC noise called CDS (correlated double sampling) processing. An example of CDS application to CMOS image sensors is found in U.S. Pat. No. 6,133,862 to Dhuse. The key principle used in the CDS method consists of sampling the node twice. The first time without charge and the second time after charge has been transferred on the node. The difference of these two readings is the desired signal without kTC noise. Unfortunately this method is not 100% efficient in removing kTC noise, requires more complicated signal processing circuits including a memory for storing the first reading, and the double sampling increases Johnson noise. In many cases the CDS technique is not directly applicable to pixels of APS sensors, which gives the CMOS sensors a competitive disadvantage in comparison to CCD image sensors, where the more sophisticated signal processing is frequently used.
The charge readout that does not generate kTC noise is based on a complete charge removal from the node. This is used, for example, in Floating Gate charge detectors or Bulk Charge Detectors (U.S. Pat. No. 5,546,438 to Hynecek). Incorporating the structure with complete charge removal capability into the pixels of CMOS image sensors is one of the key points of the present invention.
SUMMARY OF THE INVENTION
The present invention relates to Active Pixel CMOS Image Sensors (APS) employing pixels that can be readout repeatedly and do not generate kTC noise. Such sensors have an advantage in efficient signal processing and subtracting the pixel signal response nonuniformities, since the inherent pixel temporal noise is very low and can be neglected. This leads to a superior low light level sensitivity and higher overall image sensing performance.
Incorporating the Vertical Punch Through (VPT) transistor into the CMOS sensor pixels, surrounding the source of the transistor by a junction gate that is connected to it, the junction gate being further completely surrounded by an MOS gate, achieves these and other objects of the invention.
The present invention to overcome limitations in prior art by providing practical non-destructive charge detection readout system for the pixels of typical CMOS image sensors that completely removes charge from the pixels during reset and therefore does not generate kTC noise. The invention also provides practical high performance charge detection CMOS sensor pixel design that is compatible with CMOS processing, has a non destructive charge readout, complete charge removal during reset, high sensitivity, high quantum efficiency, blooming protection, and low dark current.
REFERENCES:
patent: 5546438 (1996-08-01), Hynecek
patent: 5942774 (1999-08-01), Isogai et al.
patent: 6023081 (2000-02-01), Drowley
patent: 6040592 (2000-03-01), McDaniel
patent: 6133862 (2000-10-01), Dhuse
patent: 2002/0093034 (2002-07-01), Hynecek
patent: 2002/0163042 (2002-11-01), Yamazaki et al.
Flynn Nathan J.
Isetex. Inc
Tran Tan
Vandigriff John E.
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