CMOS image sensor n-type pin-diode structure

Details CMOS image sensor n-type pin-diode structure CMOS image sensor n-type pin-diode structure

2000-06-09

2003-02-04

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

C438S007000, C438S048000, C438S057000, C438S059000, C438S510000, C438S514000, C438S519000, C257S113000, C257S184000, C257S186000, C257S290000, C257S292000

Reexamination Certificate

active

06514785

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates generally to image sensing devices and more particularly to such devices having high sensitivity photodiodes with very low dark current.
(2) Description of the Prior Art
Image sensors are utilized extensively in modern technology. U.S. Pat. No. 5,789,774 to Merrill shows a method of forming a pixel sensor cell with reduced leakage current that is achieved by eliminating field oxide from the cell and by appropriately biasing, during integration, every surface region of the cell that is not heavily doped. U.S. Pat. No. 5,841,176 to Merrill also shows a method of forming a pixel sensor with reduced leakage current, here this is achieved by utilizing a series of low doped regions to provide isolation between heavily doped regions of the cell. U.S. Pat. No. 5,719,414 to Sato et al. discloses a photodiode process using a boron or boron fluoride ion implantation into an n-type semiconductor substrate with an n-type impurity region in a rear surface. U.S. Pat. No. 5,739,065 to Lin teaches a method of fabricating a PIN photodiode.
Conventional image sensing devices often utilize junction photodiodes as the photosensitive device. The ion implants required to form these junction photodiodes are performed simultaneously with the source/drain implants of the adjacent FET and the photodiode implants are extensions of source/drain regions. This is shown in
FIG. 1
Prior Art for a lightly doped drain (LLD) n− channel FET (NFET). Region
4
is a gate oxide grown over the surface of a p-well,
2
. A polysilicon gate electrode,
6
, is formed and a first, lower dose, implant is self-aligned to the gate electrode to achieve an n− region,
14
, below the gate oxide extending to the field oxide,
10
. An implant mask,
12
, which could be photoresist, is disposed over the field oxide. Oxide spacers,
8
, are then formed and a second, higher dose, implant is self-aligned to the oxide spacers. An n+ region,
16
, is thus achieved, disposed under the n-region, separated from the gate electrode by about the thickness of the oxide spacer and extending to the field oxide. The n region of the junction photodiode thus formed is an extension of the FET drain. The characteristics of the implants forming this region, chosen to optimize the FET performance, are not likely to optimize the performance of the junction photodiode. For the photodiode, it is particularly important to choose implants that optimize sensitivity and minimize dark current.
SUMMARY OF THE INVENTION
Accordingly, it is a primary objective of the invention to provide a method of forming a CMOS image sensor that permits optimization of both the photodiode and the FET. This objective is achieved by performing the ion implantation of the photodiode separately from that of the FET and adjusting the implantation characteristics specifically to attain desired photodiode properties. A wide field region leads to high sensitivity. This can be achieved by having a wide intrinsic, or near intrinsic, region sandwiched between an n-type and p-type region. Sources of photodiode leakage generally accumulate near surfaces at imperfections where thermal charge carrier generation is enhanced. If these sources are within a minority carrier diffusion length of the field region they contribute to the dark current. When the majority carrier density is large the minority carrier diffusion length is small. Therefor by providing a sufficiently high doping density near the surface these sources of leakage are rendered ineffective.
In a preferred embodiment of the invention a partially processed n-type semiconductor substrate is provided in which a p-well or p-substrate has been formed. The surface of the p-well or p-substrate consists of a region of gate oxide bounded by field oxide. A conductive gate structure is disposed asymmetrically on the gate oxide. On one side a source/drain region can be accommodated under the gate oxide in an area bounded by the gate and the field oxide. On the other side, the area bounded by the gate and the field oxide can also accommodate a photodiode between a source/drain region and the field oxide, with some overlap of the photodiode and source/drain region. Using a mask that is open only over the gate, the source/drain regions the overlap region, a shallow, low dose, donor ion implantation is performed. Insulating spacers are then applied to the gate sidewalls by depositing an insulating layer and etching this layer with an anisotropic etch. Again using a mask that is open only over the gate, the source/drain regions and the overlap region, a deeper, higher dose, donor ion implantation is performed. LDD structures are thus attained for the source drain regions. Next, the photodiode implants are performed using a mask open only over the photodiode area and the area of overlap of the photodiode and source/drain. The first donor implant, giving rise to the field region of the photodiode, is deeper than the source/drain implants and provides a wide low-density n-type region. A high dose shallow donor implant is then performed, using the same mask, to attain an n++ region near the surface. A transparent insulating layer is now deposited.
In other preferred embodiments of the invention a lightly doped n-well is formed in the photodiode region. An n-channel transistor is then fabricated, preferably having the LDD structure. A high dose shall donor implant is performed followed by deposition of a transparent insulating layer.
Lightly doped drain structures for PMOS transistors on the substrate are achieved by first performing a shallow, low dose, acceptor ion implant. Insulating spacers on the gate are then fabricated concurrent with the insulating spacers of the NMOS transistors, including those of the image sensor. A deeper acceptor ion implant follows which is done before a shallow high dose acceptor implant. Deposition of a transparent insulating layer follows.
A method of forming an image sensor is disclosed. A partially processed semiconductor wafer is provide, containing p-type and/or n-type regions which are bounded by isolation regions and with gate oxide layers grown on the surfaces upon which gate electrode structures are disposed, some of said gate electrode structures will serve as gate electrodes of image sensor transistors. Ions are implanted to form source/drain structures about the said gate electrode structures. To form photodiodes ions are implanted in two steps overlapping a source/drain region and separated from the bird's beak. A deeper implant provides a low charge carrier density region and a shallow implant provides a high charge carrier density region near the surface. A blanket transparent insulating layer is deposited.


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