CMOS image sensor having row decoder capable of shutter...

Details CMOS image sensor having row decoder capable of shutter... CMOS image sensor having row decoder capable of shutter...

2005-07-19

2005-07-19

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189080

Reexamination Certificate

active

06920078

ABSTRACT:
A CMOS image sensor having a row decoder capable of shutter timing control is provided, the row decoder addressing to a plurality of pixels arranged in rows and columns in a CMOS image sensor and including a plurality of unit arrays, wherein the unit arrays include a first NAND gate for generating a reset gate signal in response to an address signal and a reset signal, a second NAND gate for generating a selection gate signal in response to the address signal and a selection signal, a latch for resetting an output thereof in response to an address latch signal and latching the address signal as the output in response to the address latch signal and the address signal, a third NAND gate for receiving the address signal and a transmitted signal, a fourth NAND gate for receiving the output of the latch and a shutter transmitted signal, and an OR gate for receiving the outputs of the third and fourth NAND gates and generating a transmitted gate signal; wherein shuttering of a row address is latched in accordance with the blank interval of the horizontal synchronization signal using latches of the row decoder, and the shuttering operation is performed sequentially increasing the shuttering row address by 1, the invalid data that are not shuttered are thereby prevented from being generated though the row shutter value is changed suddenly.

REFERENCES:
patent: 5912857 (1999-06-01), Kim et al.
patent: 6198686 (2001-03-01), Takita et al.
patent: 6243319 (2001-06-01), Yokozeki
patent: 6320799 (2001-11-01), Miyazaki et al.
patent: 2002/0089597 (2002-07-01), Pearson
patent: 19728 (2000-04-01), None
English Abstract Only.

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