CMOS image sensor having common outputting transistors and...

Details CMOS image sensor having common outputting transistors and... CMOS image sensor having common outputting transistors and...

1999-05-06

2004-05-04

Garber, Wendy R. (Department: 2612)

Television

Camera, system and detail

Solid-state image sensor

C348S294000, C348S302000, C348S241000

Reexamination Certificate

active

06731335

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a CMOS (Complementary Metal Oxide Semiconductor) image sensor; and, more particularly, to a pixel array of the CMOS image sensor and a method for driving the pixel array.
DESCRIPTION OF THE PRIOR ART
Generally, an image sensor is an apparatus to capture images using light sensing semiconductor materials. Since brightness and wavelength of light from an object are different in their amount according to the reflection area, electrical signals from pixels are different from one another. These electrical signals are converted into digital signals, which can be processed in a digital circuit, by an analogue-to-digital converter. Thus, the image sensor needs a pixel array having tens to hundreds of thousands of pixels, a converter for converting analogue voltages into digital voltages, hundreds to thousands of storage devices and so on.
Referring to
FIG. 1
, a conventional CMOS image sensor includes a control and interface unit
10
, a pixel array
20
having a plurality of CMOS image sensing elements, and a single slope AD converter
30
. The single slope AD converter
30
also includes a ramp voltage generator
31
for generating a reference voltage, a comparator (operational amplifier)
32
for comparing the ramp voltage with an analogue signal from the pixel array
20
and a double buffer
40
.
The control and interface unit
10
controls the CMOS image sensor by controlling an integration time, scan addresses, operation modes, a frame rate, a bank and a clock division and acts as an interface with an external system. The pixel array
20
consisting of N×M unit pixels having excellent light sensitivity senses images from an object. Each pixel in the pixel array
20
includes a transfer transistor, a reset transistor and a select transistor. The single slope AD converter
30
converts analogue signals from the pixels array
20
into digital signals. This AD conversion is carried out by comparing the ramp voltage with the analogue signals. The comparator
32
searches for a point at which the analogue signals are the same as the falling ramp voltage with a predetermined slope. When the ramp voltage is generated and then starts falling, the control and interface unit
10
generated count signals to count the degree of the voltage drop. For example, the ramp voltage starting the voltage drop, the converted digital value may be “20” in the case where the analogue signals are the same as the falling ramp voltage at 20 clocks of the control and interface unit
10
. This converted digital value is stored in the double buffer
40
as digital data.
Where the CMOS image sensor supports the correlated double sampling (hereinafter, referred to as a CDS) in order to generate images of high quality, unit pixels
100
and
120
in the pixel array include a photodiode and four transistors, respectively, as shown in FIG.
2
. Also, the four transistors in the unit pixel
100
include a transfer transistor M
21
, a reset transistor M
11
, a drive transistor M
31
and a select transistor M
41
. The transfer transistor M
21
transfers photoelectric charges generated in the photodiode
101
to sensing node A, the reset transistor M
11
resets sensing node A in order to sense a next signal, the drive transistor M
31
acts as a source follower and the select transistor M
41
outputs the digital data to an output terminal in response to the address signals.
In accordance with the CDS, the unit pixel
100
obtains a voltage corresponding to a reset level by turning on the reset transistor M
11
and turning off the transfer transistor M
21
. Also, the unit pixel
100
obtains a data level voltage by turning off the transfer transistor M
21
in a turn-off state of the reset transistor M
11
and reading out photoelectric charges generated in the photodiode
101
. An offset, which is caused by the unit pixel
100
and the comparator
32
, may be removed by subtracting the data level from the reset level. This removal of the offset is essential to the CDS. That is, by removing an unexpected voltage in the unit pixel
100
, it is possible to obtain a net image data value.
FIG. 3
shows a timing chart illustrating control signals to control transistors of the unit pixel shown in FIG.
2
. The operation of the unit pixel
100
will be described with reference to FIG.
3
.
1) In section “A” of
FIG. 3
, the transfer transistor M
21
and the reset transistor M
11
are turned on and the select transistor M
41
is turned off, so that the photodiode
101
is fully depleted.
2) In section “B”, the turned-on transfer transistor M
21
is turned off, so that the photodiode
101
receives light from an object, generates photoelectric charges and integrates the photoelectric charges (Section “B” continues on regardless of the states of the reset transistor M
11
and the selector transistor M
41
, until the transfer transistor M
21
is again turned on).
3) In section “C”, the reset transistor M
11
and the transfer transistor M
21
keep on a turn-on state and a turn-off state, respectively, and the select transistor M
41
is turned on, so that reset voltage level is outputted through the select transistor M
41
and the drive transistor M
31
driven by the voltage level at sensing node A.
4) In section “D”, the resent transistor M
11
is turned off and then the reset voltage level generated in section “C” is settled.
5) In section “E”, the reset voltage level of section “D” is sampled.
6) In section “F”, the reset transistor M
11
and the select transistor M
41
keep on a turn-off state and a turn-on state, respectively, and the transfer transistor M
21
is turned on, so that a data voltage level corresponding to photoelectric charges integrated in the photodiode
101
during the time of section “B”, is transferred to the output terminal through the sensing node A, the drive transistor M
31
and the select transistor M
41
.
7) In section “G”, the transfer transistor M
21
is turned off and then the data voltage level generated in section “F” is settled.
8) In section “H”, the data voltage level of section “G” is sampled. The reset voltage level and the data voltage level sampled in sections “E” and “F”, respectively, are outputted to the AD converter
30
(
FIG. 1
) and converted into two digital signals. The difference of two digital signals becomes an output image value of the CMOS image sensor with respect to an image inputted from the photodiode
101
(FIG.
1
).
This conventional unit pixel employs four transistors per pixel in order to support the CDS, thus increasing the chip size of the CMOS image sensor.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a CMOS image sensor that may reduce its chip area by decreasing the number of transistor for a pixel array and a method for driving the CMOS image sensor.
In accordance with an aspect of the present invention, there is provided a CMOS (Complementary Metal Oxide Semiconductor) image sensor, comprising: a unit pixel, the unit pixel including: a plurality of photodiodes receiving incident light form an object for generating photoelectric charges; a plurality of transferring means corresponding to the plurality of photodiodes, for transferring the photoelectric charges from the plurality of photodiodes to a single sensing node in response to control signals from an external controller, wherein the control signals controls the plurality of transferring means so that the photoelectric charges from the plurality of photodiodes are selectively transferred to the single sensing node; a common reset means for resetting the single sensing node, wherein the reset means determines reset levels of the single sensing node corresponding to each of the plurality of photodiodes; and a common outputting means for outputting electrical signals corresponding to voltage levels of the single sensing node, wherein the CMOS image sensor samples the electrical signals through the correlated double sampling and then outputs a final image value to the external device.
In accordance with anothe

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