Patent
1988-04-08
1990-04-24
Hille, Rolf
357 64, 357 16, 357 86, H01L 2702, H01L 29167, H01L 29161
Patent
active
049203967
ABSTRACT:
In order to improve latchup withstanding capability, a CMOS device is provided with at least one recombination layer which is buried in either or both substrate regions of a pMOS and a nMOS at such a position that a depletion layer formed at a pn junction between both substrate regions of the pMOS and nMOS does not reach the recombination layer. The recombination layer is a polycrystalline silicon or amorphous silicon layer having plentiful carrier recombination centers, or a layer having plentiful traps formed by ion implantation, or a layer of a compound semiconductor having a small band gap.
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Mihara Teruyoshi
Shinohara Toshiro
Yao Kenji
Hille Rolf
Limanek Robert P.
Nissan Motor Company Limited
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