CMOS gate array with orthagonal gates

Details CMOS gate array with orthagonal gates CMOS gate array with orthagonal gates

1987-01-21

1989-03-28

Larkins, William D.

357 45, H01L 2978, H01L 2704

Patent

active

048168874

ABSTRACT:
A masterslice semiconductor device comprised of basic cells having additional transistors formed adjacent to the longitudinal end of one or more pairs of transistors which have a configuration almost the same as in the ordinary basic cell. The basic cells are arranged along columns of the semiconductor substrate they are formed in, and constitute a plurality of basic cell arrays. Each of the additional transistors occupies an individual conduction region for the source and drain and is provided with an individual gate electrode which extends to be in line with or perpendicularly to the extension line of the gate of the transistor pair. The additional transistors occupy the space between adjacent basic cell arrays which are, in the prior art masterslice semiconductor device, exclusively used for distributing wiring lines, and accordingly the width of the space is decreased. Because of the versatility of the additional transistors, and the reduced distance between adjacent basic cell arrays, a unit cell can be organized by using the basic cells belonging to adjacent basic cell arrays. The additional transistors are made inactive when the region which they occupy must be exclusively used for distributing interconnecting lines.

REFERENCES:
patent: 4412237 (1983-10-01), Matsumura et al.
patent: 4513307 (1985-04-01), Brown
C. Cohen, "Gate Array Needs Fewer Gates for RAM", Electronics International, vol. 56, No. 3, Feb. 1983, pp. 89-90 (?), New York, US.

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