CMOS gate array configured as a SRAM with load resistors over ga

Details CMOS gate array configured as a SRAM with load resistors over ga CMOS gate array configured as a SRAM with load resistors over ga

1991-02-08

1993-07-06

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

257211, 257369, 257381, 257904, H01L 2710, H01L 2904, H01L 2702

Patent

active

052256936

ABSTRACT:
In a semiconductor memory serving as an SRAM mounted on a CMOS gate array, a memory cell is constituted by a pair of transistors of a first conductivity type channel and a pair of transistors of a second conductivity type channel of the CMOS gate array and load resistances formed on the gate electrodes of the pair of transistors of the first conductivity type channel. Although the CMOS gate array is used, a memory cell area is small and a large capacity can be easily obtained.

REFERENCES:
patent: 4541006 (1985-09-01), Ariizumi et al.
patent: 4862241 (1989-08-01), Ashida et al.
IEEE Journal of Solid-State Circuits, "A 0/8-.mu.m CMOS Technology for High-Performance ASIC Memory and Channelless Gate Array", Apr. 1989, No. 2, pp. 380-387.

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