CMOS gain boosting scheme using pole isolation technique

Details CMOS gain boosting scheme using pole isolation technique CMOS gain boosting scheme using pole isolation technique

1998-11-25

2001-01-23

Mottola, Steven J. (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S311000

Reexamination Certificate

active

06177838

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to complementary metal oxide semiconductor (CMOS) circuitry, and more specifically to a gain enhanced cascoded CMOS operational amplifier circuit providing faster settling time without sacrificing stability and accuracy.
2. Description of the Prior Art
Analog signal processing circuits having CMOS operational amplifier (op-amp) circuits include switched-capacitor filters, algorithmic A/D converters, sigma-delta converters, sample- and hold amplifiers, and pipeline A/D converters. Analog signal processing applications typically require op-amp circuits having a high gain high accuracy analog signal processing systems typically require a gain of 60 dB to 100 dB. Gain is typically limited in CMOS op-amp circuits due to device characteristics. However, high gain is only one of several important op-amp circuit design parameters which further include accuracy and stability which are related to linearity and phase margin. In many cases, the speed and accuracy of a CMOS analog signal processing system is determined by the settling behavior of a CMOS operational amplifier circuit included therein As explained below, fast settling time in an op-amp circuit requires a high unity-gain frequency and preferably a single-pole settling behavior.
FIG. 1A
shows a schematic diagram at
10
of a single transistor CMOS operational amplifier (op-amp) circuit including: a current source
12
having a terminal
14
connected to a system voltage source VDD, and an opposite terminal
16
connected to a node
18
; an NMOS transistor
20
having a drain
22
connected to node
18
, a gate
24
connected to receive an input voltage V
i
, and a source
26
connected to a node
28
; and a load capacitor
30
having a terminal connected to node
18
, and an opposite terminal connected to node
28
. An output voltage V
O
is developed across the load capacitor
30
between nodes
18
and
28
, in response to the input voltage V
i
provided to gate
24
of the transistor
20
.
FIG. 1B
shows a schematic diagram at
40
of an AC small signal equivalent circuit of the single transistor CMOS op-amp circuit
10
(FIG.
1
A). The equivalent circuit
40
includes: a voltage controlled current source
42
having a first terminal connected to a node
44
, and an opposite terminal connected to a node
46
; an output resistance element
48
having an output impedance value r
o
, and having a terminal connected to node
44
, and an opposite terminal connected to node
46
; and a load capacitive element
50
having a load capacitance value C
L
, and having a terminal connected to node
44
, and an opposite terminal connected to node
46
. The input voltage V
i
is represented across a terminal
52
and node
46
, and the output voltage V
O
is represented across nodes
44
and
46
. The output impedance value r
o
represents the output impedance of the op-amp circuit
10
(
FIG. 1A
) looking into the output node
18
(FIG.
1
A). The voltage controlled current source
42
provides a current, i, having a value expressed according to Relationship (1), below,
i
=(
g
m
*V
i
)  (1)
wherein g
m
represents the transconductance of the NMOS transistor
20
(FIG.
1
A).
The DC gain, A
DC
, of the op-amp circuit
10
(
FIG. 1A
) may be generally expressed in accordance with Relationship (2), below.
A
DC
=V
out
/V
in
=(
g
m
* r
0
)  (2)
The gain as a function of frequency of the circuit
10
(
FIG. 1A
) may be generally expressed in accordance with Relationship (3), below,
A
(
f
)=
A
DC
/(1+
j*f/f
0
)  (3)
wherein f
0
, is the pole frequency of the circuit
10
(
FIG. 1A
) which is equal to 1/(2*&pgr;*r
o
*C
L
).
FIG. 1C
shows a bode plot at
60
representing the gain
61
, or frequency response of the single transistor op-amp circuit
10
(FIG.
1
A). The depicted bode plot includes an AY-axis
62
representing the log of the gain of the single transistor op-amp expressed in decibels (dB), and an X-axis
64
representing the log of frequency. Between DC (f=0) and a first pole frequency f
0
, the gain
61
is approximately equal to A
DC
. At the first pole frequency f
0
, the gain begins to roll off at negative 20 dB/decade, at a slope of −1 on the log—log scale. The first pole frequency, which is associated with the load capacitance C
L
and output impedance r
o
of the circuit
10
(FIG.
1
A), is also commonly referred to as the negative 3 dB frequency point, or the negative 3 dB bandwidth. At a unity gain frequency f
u
, the gain
61
of the op-amp circuit
10
(
FIG. 1A
) is equal to 0 dB, which corresponds with a unity gain value. The unity gain frequency f
u
is equal to (A
DC
*f
0
) for the single pole op-amp circuit
10
(FIG.
1
A).
Due to a short channel effect in modern sub-micron CMOS processes, the gain provided by the single transistor CMOS op-amp circuit
10
(
FIG. 1A
) is limited to approximately 20 to 25 dB. However, gain is only one important design parameter. Speed and accuracy are also important properties of op-amp circuits. Typically, methods for increasing the gain of an op-amp circuit give rise to higher order poles.
Because of the demand for increased clock rates in switched capacitance circuits, fast-settling time is required for accuracy in op-amp circuits. Fast-settling time requires a high unity-gain frequency and preferably a single-pole settling behavior, whereas accurate settling requires a high DC-gain. The realization of a CMOS op-amp circuit that combines high DC-gain with high unity-gain frequency has been a difficult problem. A high DC gain is typically achieved using multistage designs with long-channel devices biased at low current levels, whereas a high unity-gain frequency is typically achieved using a single-stage design with short-channel devices biased at high current levels. Future processes with sub-micron channel length will enable the realization of higher unity-gain frequencies. However, the intrinsic MOS transistor gain, (g
m
*r
o
), will then be lower, and the problem of achieving sufficient DC-gain becomes even more difficult.
Several circuit design approaches have been developed to circumvent this problem. Cascoding is a well-known means to enhance the DC-gain of an amplifier without severely degrading the high-frequency performance. The result is a DC-gain that is proportional to the square of the intrinsic MOS transistor gain (g
m
*r
o
). However, cascoding does not provide optimal phase margin because power supply levels are decreasing in modern CMOS devices, head room between power supply rails is decreasing. The technique of cascoding is not amenable to decreased head room.
FIG. 2A
shows a schematic diagram at
80
of a cascoded CMOS gain stage. The depicted gain stage
80
includes: a current source
82
having a terminal
84
connected to a system voltage source VDD, and an opposite terminal
86
connected to a node
88
; a cascoded transistor
90
having a drain
92
connected to node
88
, a gate
94
connected to receive a reference voltage V
ref
, and a source
96
connected to a node
98
; an input transistor
100
having a drain
102
connected to node
98
, a gate
104
coupled to receive an input voltage V
i
, and a source
106
connected to VSS. In the depicted circuit, both the cascoded transistor
90
and the input transistor
100
are NMOS transistors. The gain stage
80
further includes: a load capacitor
110
having a capacitance value C
L
, and having a terminal connected to node
88
, and an opposite terminal connected to VSS; and a parasitic capacitance element
112
having a capacitance value C
P
, and having a terminal connected to node
98
, and an opposite terminal connected to VSS.
An increased gain is achieved in the cascoded CMOS gain stage
80
over the single transistor op-amp
10
(
FIG. 1A
) in accordance with the method of cascading which increases the gain of an op-amp circuit by increasing the output impedance of the op-amp circuit. The DC-gain of an op-amp circuit is

Affiliated with

Also associated with

Rating

CMOS gain boosting scheme using pole isolation technique does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS gain boosting scheme using pole isolation technique, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS gain boosting scheme using pole isolation technique will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2455038