CMOS full adder circuit with pair of carry signal lines

Details CMOS full adder circuit with pair of carry signal lines CMOS full adder circuit with pair of carry signal lines

1994-10-04

1997-01-21

Mai, Tan V.

Boots, shoes, and leggings

364784, G06F 750

Patent

active

055965202

ABSTRACT:
A full adder circuit has a plurality of full adders each provided for each bit. Each full adder has: a calculation block (31a) responsive to a first carry signal (C) given by a preceding stage bit as a differential signal and two external input data (A1, B1) to be added at a present stage bit, for outputting addition data calculated on the basis of the first carry signal and the external input data as two differential signals, and further outputting a second carry signal (/C) to a succeeding bit as a differential signal indicative of whether a carry is generated by the present stage bit or not. Each full adder also has a latch type sense amplifier (16a) for outputting an addition result (SUM) of the present stage bit, after having differentially amplified and latched the addition data outputted by the calculation block. Since the addition operation is made on the basis of the carry signals (C and /C) of a minute potential difference (before amplification), it is possible to shorten the required charging time and to reduce the current consumption. In addition, since the sense amplifiers (16a) are provided with the latch function (18a), it is possible to control the differential amplification operation and the latch operation on the basis of a common sense amplifier activating signal (SAB), so that the number of elements can be reduced.

REFERENCES:
patent: 4357675 (1982-11-01), Freyman
patent: 4802112 (1989-01-01), Yoshida et al.
patent: 4807176 (1989-02-01), Yamada et al.
patent: 4858167 (1989-08-01), Simpson et al.

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