CMOS full adder circuit

Details CMOS full adder circuit CMOS full adder circuit

1985-01-04

1987-08-25

Malzahn, David H.

Boots, shoes, and leggings

G06F 750

Patent

active

046897631

ABSTRACT:
A full adder circuit includes a sum circuit section, a carry-out circuit section, a carry-in circuit section; and an output circuit section. The sum circuit section includes a plurality of N-channel type MOS transistors having their gates adapted to receive true and complement binary addend signals of an ith order. The sum circuit section also includes a plurality of N-channel type MOS transistors having their gates adapted to receive true and complement binary augend signals of an ith order. The carry-out circuit section includes a plurality of N-channel type MOS transistors having their gates adapted to receive true and complement binary addend signals of an ith order. The carry-out circuit section also includes a plurality of N-channel MOS transistors having their gates adapted to receive true and complement binary augend signals of an ith order. The carry-in circuit section is formed of a plurality of N-channel type MOS transistors having their gates adapted to receive true and complement carry-in signals of an ith-1 order. The output circuit section includes a first pair of cross-coupled P-channel type MOS transistors connected to the sum circuit section and having their drains connected to respective true and complement sum output terminals. The output circuit section further includes a second pair of cross-coupled P-channel type MOS transistors connected to the carry-out circuit section and having their drains connected to respective true and complement carry-out terminals. All of the transistors are arranged on an integrated circuit substrate with topological regularity.

REFERENCES:
patent: 4215418 (1980-07-01), Muramatsu
patent: 4471454 (1984-09-01), Dearden et al.
patent: 4583192 (1986-04-01), Cieslak
patent: 4601007 (1986-07-01), Uya et al.
patent: 4621338 (1986-11-01), Uhlenhoff

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