CMOS Four-transistor reset/set latch

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307288, 357 23, H03K 3356, H01L 2978

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active

044840888

ABSTRACT:
An R/S latch circuit employing four IGFETs, one pair of P-channel IGFETs, and another pair of N-channel IGFETs. The P-channel IGFETs have channels respectively connecting Q and Q data output nodes to +V.sub.DD, and gates cross-connected to the opposite data output nodes. The N-channel IGFETs have channels respectively connecting the Q and Q data output nodes to ground, and have gates which respectively comprise the Reset (R) and Set (S) data inputs. A pair of high impedance leakage current paths may also be provided respectively electrically connecting the Q and Q data output nodes to ground. Particular integrated circuit R/S latch structures are disclosed.

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Gaensslen et al., "FET Memory Cell", IBM Tech. Discl. Bull.; vol. 13, No. 7, pp. 1751; 12/1970.
Lee, "Race-Free Level Sensitive Master-Slave Latch Utilizing a Single Phase Clock"; IBM Tech. Discl. Bull., vol. 20, No. 1, pp. 263-264; 6/77.

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