CMOS Flip-flop

Details CMOS Flip-flop CMOS Flip-flop

1983-06-22

1985-11-19

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307452, 307583, 307585, 307269, H03K 3289, H03K 1704, H03K 19003

Patent

active

045544670

ABSTRACT:
A static CMOS delayed flip-flop uses only a weak P channel transistor for reinforcing a logic high at a control node while using a pair of series connected N channel transistors for reinforcing a logic low at the control node. Only a single P channel device is required because it can be made to have sufficiently low gain at a relatively small device size so that the control node can have it logic state switched by an N channel device of comparable size.

REFERENCES:
patent: T955006 (1977-02-01), Cavaliere et al.
patent: 3577166 (1971-05-01), Yung
patent: 3676702 (1972-07-01), McGrogan, Jr.
patent: 3851189 (1974-11-01), Moyer
patent: 3964031 (1976-06-01), Eaton, Jr.
patent: 4080539 (1978-03-01), Stewart
patent: 4104860 (1978-08-01), Stickel
patent: 4216360 (1980-08-01), Stewart
patent: 4239994 (1980-12-01), Stewart
patent: 4250406 (1981-02-01), Alaspa
patent: 4484087 (1984-11-01), Mazin et al.
Suzuki et al., "Clocked CMOS Calculator Circuitry", IEEE Journal of Solid State Circuits, vol. SC-8, No. 6, Dec. 1973.

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