Electrical transmission or interconnection systems – Personnel safety or limit control features – Interlock
Patent
1978-05-23
1979-09-18
Anagnos, Larry N.
Electrical transmission or interconnection systems
Personnel safety or limit control features
Interlock
307200B, 307213, 307251, 357 42, 328167, H03K 3353, H03K 1716, H03K 1760, H01L 2978
Patent
active
041684427
ABSTRACT:
A CMOS FET device which comprises an N type semiconductor substrate; a P type well layer formed in the N type semiconductor substrate; a p-channel type MOS transistor provided in the N type semiconductor substrate; an n-channel type MOS transistor formed in the P type well layer; and a noise-absorbing capacitor provided at the input or output terminal of the MOS transistor or at a power supply section.
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Dennehy, "Non-Latching Integrated Circuits"; RCA Technical Notes (pub.) TN No.: 876; 2/12/71; 4 pp.
Staples, "Electrical Noise Spike Suppression"; IBM Tech. Discl. Bull.; vol. 15, No. 10, p. 3208; 3/73.
Clapper, "Bandpass Filter Using Differential Amplifier", IBM Tech. Discl. Bull.; vol. 14, No. 3, pp. 815-816, 8/71.
Satou Kazuo
Suzuki Yasoji
Ueno Mitsuhiko
Anagnos Larry N.
Tokyo Shibaura Electric Co. Ltd.
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