CMOS fabrication process utilizing special transistor...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – With current flow along specified crystal axis

Reexamination Certificate

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Details

C257S358000, C257S369000, C257S254000, C257S417000, C257S418000, C438S199000, C438S050000, C438S052000, C438S053000

Reexamination Certificate

active

09727296

ABSTRACT:
Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the <100> direction. Additionally, longitudinal tensile stress is applied to the channels.

REFERENCES:
patent: 3965453 (1976-06-01), Seidel et al.
patent: 5171703 (1992-12-01), Lin et al.
patent: 5981325 (1999-11-01), Hung
patent: 6046494 (2000-04-01), Brigham et al.
patent: 6897526 (2005-05-01), Miyanaga et al.
patent: 0703 628 (1996-03-01), None
patent: 928562 (1963-06-01), None
patent: 1222251 (1971-02-01), None
patent: 1-162362 (1989-06-01), None
Sayama et al. Effect of <100> Channel direction for high performance SCE immune pMOSFET with less than 0.15um gate length).
Toshihiro, Matsuda, et al., “Electrical Characteristics of 0° /±45° /90° -Orientation CMOSFET with Source/Drain Fabricated by Various Ion-Implantation Methods”,IEEE Transactions on Electronic Devices, vol. 46, No. 4, Apr. 1999.
Sayama, H., et al., “Effect of <100> Channel Direction for High Performance SCE Immune pMOSFET with Less Than 0.15 μm Gate Length”,IEEE, 1999.
Welser, J. et al, “Strain Dependence of the Performance Enhancement in Strained-Sin-MOSFETs”,IEEE, 1994.
Scott, Gregory, et al, “The Effect of Stress and Dopant Redistribution on Trench-Isolated Narrow Devices”,In Challenges in Process Integration and Device Technology, Proceedingof SPIE vol. 4181, 2000.
Scott, Gregory, et al, “NMOS Drive Current Reduction Caused by Transistor Layout and Trench Isolation Induced Stress”,IEEE, 1999.
PCT International Search Report, Aug. 26, 2002.

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