CMOS ESD protection circuit with parasitic SCR structures

Details CMOS ESD protection circuit with parasitic SCR structures CMOS ESD protection circuit with parasitic SCR structures

1991-03-25

1992-08-18

Lee, John D.

H01L 2702

Patent

active

051404010

ABSTRACT:
A circuit for protecting a CMOS device against execssive voltages has two SCR circuits in which the bipolar transistors are formed as parasitic devices. One SCR circuit is connected between a line to be protected and one power supply point and the other SCR circuit is connected between the line to be protected and the other power supply point. The power supply points form sinks for currents associated with excessive voltages, and they form reference potential points for establishing the voltage at which an SCR turns on. A semiconductor device having an n-substrate has three p-wells. The center p-well (as seen in section) forms part of two vertical transistors, one for each of the two SCR's. Each outer p-well cooperates with the center p-well and the intervening substrate to form a lateral transistor for one of the SCR's. These transistors use shared semiconductor regions that establish the base to collector interconnections of an SCR. These regions and other structures also form an FET and a diode in each SCR circuit that turn on the SCR in response to an excessive voltage.

REFERENCES:
patent: 4937647 (1990-06-01), Sutton

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