CMOS EEPROM cell with tunneling window in the read path

Details CMOS EEPROM cell with tunneling window in the read path CMOS EEPROM cell with tunneling window in the read path

1995-11-06

1996-12-24

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular connection

36518518, 36518526, 326 45, G11C 1602

Patent

active

055879454

ABSTRACT:
A CMOS memory cell including PMOS and NMOS transistors with a common floating gate. The CMOS memory cell includes a first capacitor connecting a first control voltage to the common floating gate and a second tunneling capacitor connected from the common floating gate to the source of the NMOS transistor. The tunneling capacitor includes a tunneling oxide region utilized to charge or discharge the floating gate during program or erase. The CMOS cell further includes a pass transistor with a source to drain path connecting the source of the NMOS transistor to a second control voltage.

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patent: 5404328 (1995-04-01), Takemae

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