Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1991-03-27
1992-11-24
Hudspeth, David
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307443, 307451, 307360, H03R 19094
Patent
active
051665581
ABSTRACT:
According to this invention, there is disclosed an output circuit including a MOS transistor having two current paths inserted between a power source voltage and an output terminal, a MOS transistor having two current paths inserted between a power source voltage and the output terminal, a differential amplifier for comparing a reference voltage with an voltage at the output terminal, a differential amplifier for comparing a reference voltage lower than the reference voltage with the voltage at the output terminal, an input terminal for applying an input voltage, a logic gate for receiving an output from the differential amplifier and the input voltage, the logic gate having an output terminal connected to a gate of the MOS transistor, and a logic gate for receiving an output from the differential amplifier and the input voltage, the logic gate having an output terminal connected to a gate of the MOS transistor.
REFERENCES:
patent: 4284910 (1981-08-01), Hofmann et al.
patent: 4691127 (1987-09-01), Huizer
patent: 4873673 (1989-10-01), Hori et al.
patent: 4947061 (1990-08-01), Metz et al.
patent: 4992677 (1991-02-01), Ishibashi et al.
patent: 5003205 (1991-03-01), Kohda et al.
patent: 5038058 (1991-08-01), Wang
patent: 5043604 (1991-08-01), Komaki
patent: 5047657 (1991-09-01), Seevinck et al.
patent: 5047663 (1991-09-01), Lee et al.
Stefan R. Meier et al., "A 2-.mu. CMOS Digital Adaptive Equalizer Chip for QAM Digital Radio Modems", IEEE Journal of Solid-State Circuits, vol. 23, No. 5, pp. 1212-1217 (Oct. 1988).
Mark Pedersen, Peter Metz, "Session 15: High-Speed Digital Circuits, FAM 15.3; A CMOS to 100K ECL Interface Circuit", 1989 IEEE International Solid-State Conference, pp. 226-227.
M. Steyaert et al., "A Full 1.2 .mu.m CMOS ECL-CMOS-ECL Converter With Subnanosecond Settling Times", IEEE 1990 Custom Integrated Circuits Conference, pp. 11.4.1-11.4.4.
Michel S. J. Steyaert et al., "ECL-CMOS and CMOS-ECL Interface in Data 1.2-.mu.m CMOS for 150 MHz Digital ECL Data Transmission Systems", IEEE Journal of Solid-State Circuits, vol. 26, No. 1 (Jan. 1991).
Hudspeth David
Kabushiki Kaisha Toshiba
LandOfFree
CMOS ECL/TTL output circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with CMOS ECL/TTL output circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS ECL/TTL output circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-924232