Static information storage and retrieval – Addressing
Patent
1985-10-01
1987-02-10
Anagnos, Larry N.
Static information storage and retrieval
Addressing
307449, 307475, 365185, G11C 800, H03K 19096
Patent
active
046427988
ABSTRACT:
A static decoding circuit which may be utilized with E.sup.2 PROM arrays. The circuit utilizes predecoded address signals to generate signals to the word lines in read, program, erase and bulk erase modes. The circuit includes a low voltage to high voltage converter, CMOS switches and post decoders which include a p-channel device so that individual row lines may be erased as well as all the row lines. In the read mode, the selected word line goes to VCC and other go to zero. In the programming mode, the selected word line goes to VPP and the selected word line goes to zero and the unselected word lines go to VPP. In the bulk erase mode, all the word lines go to zero.
REFERENCES:
patent: 4130890 (1978-12-01), Adam
patent: 4200917 (1980-04-01), Moench
patent: 4264828 (1981-04-01), Perlegos et al.
patent: 4344005 (1982-08-01), Stewart
patent: 4374430 (1983-02-01), Higuchi
patent: 4387447 (1983-06-01), Klaas et al.
patent: 4455629 (1984-06-01), Suzuki et al.
patent: 4477739 (1984-10-01), Proebsting et al.
Muller et al., "An 8192-Bit Electrically Alterable ROM Employing a One-Transistor Cell with Floating Gate", IEEE-JSSC, vol. SC-12, No. 5, pp. 507-514, 10/1977.
Ellis, "Decoded Isolation Device for Decoders", IBM-TDB; vol. 26, No. 12, pp. 6652-6653; 5/1984.
Anagnos Larry N.
Intel Corporation
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