CMOS Dynamic RAM cell and method of fabrication

Details CMOS Dynamic RAM cell and method of fabrication CMOS Dynamic RAM cell and method of fabrication

1980-09-02

1982-12-14

Munson, Gene M.

357 41, H01L 2978, H01L 2702

Patent

active

043640753

ABSTRACT:
A high density CMOS dynamic RAM cell comprising a transistor and capacitance means formed in an n-well is disclosed. The capacitance means includes a polysilicon plate member disposed above a p-type region formed in the n-well. A buried contact, extending from the plate member, pierces the p-type region and contacts the well. In addition to the capacitance associated with the plate member, p-type region and well, capacitance is obtained between the side walls of the n-type regions and p-type regions.

REFERENCES:
patent: 4158238 (1979-06-01), Erb
Masters "Reduction of Alpha-Induced Soft Errors in Dynamic Memories", IBM Tech. Disclosure Bulletin, vol. 22 (1/80), pp.3208-3209.
Brack et al., "Prevention of .alpha.-Particle Induced Fails in Dynamic Memories", IBM Tech. Disclosure Bulletin, vol. 22, (2/80), p. 4106.
Sugerman et al., "Semiconductor Device Structure with Low Soft Error Rate", IBM Tech. Disclosure Bulletin, vol. 23 (7/80), pp. 616-617.
Dockerty et al., "Alpha Particle Sensitivity Reduction", IBM Tech. Disclosure Bulletin, vol. 23, (9/80), pp. 1433-1434.

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