CMOS dual-stage differential receiver-amplifer

Details CMOS dual-stage differential receiver-amplifer CMOS dual-stage differential receiver-amplifer

2002-02-08

2003-08-12

Mottola, Steven J. (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

Reexamination Certificate

active

06605997

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to communication receivers, and in particular to CMOS differential amplifier-receivers.
2. Description of the Related Art
Differential amplifier-receivers receive two input signals and produce an output signal that is a function of the difference in values of the two input signals. Differential amplifiers are used to amplify analog, as well as digital signals, and can be used in various implementations to provide an output from the amplifier in response to differential inputs. They can be readily adapted to function as an operational amplifier, a comparator, a sense amplifier and as a front-end buffer stage for another circuit. One type of differential amplifier employs Complimentary metal-oxide semiconductor (CMOS) integrated circuits. CMOS differential amplifiers are frequently used as communication receivers in systems with large inter-connection distances. CMOS differential amplifiers are particularly useful in these environments because of their strong capabilities in common-mode, low voltage, and high speed operation.
A common technique for improving the common-mode input range of a CMOS differential amplifier is to include a self-bias feature such as that described in U.S. Pat. No. 4,958,133, issued to Bazes, which discloses complimentary pairs of transistors that are symmetrically configured. A strong common-mode rejection is provided because of the self-biasing scheme. This provides an extended range of common-mode input voltages, but at the same time provides a high gain in differential-mode amplification. Because of the biasing scheme, negative feedback is provided internally within the amplifier to provide the low sensitivity to variations.
However, a performance problem arises when using a CMOS complimentary self-bias differential amplifier as a differential receiver. This problem is seen by reviewing the well-established and commonly used circuit design for a CMOS complimentary self-biased differential amplifier. The typical design has complementary input signal paths having corresponding symmetrical transistors matched to have the same characteristics. The primary difference between the symmetrical paths is that one input of the differential input pair is coupled to the drains of the common-bias circuit, which have very little voltage swing when an input differential is applied, and the second differential input is coupled to the drains of the output driver, which has a relatively large voltage swing.
As will be appreciated by those skilled in the art, the large voltage swings on the output have a feedback effect (known as the “Miller effect”) through the drain of the input transistor that influences the input impedance for that differential input. As is well known in the art, the “Miller effect” is the deterioration of the effective input impedance caused by the presence of feedback from the output port to the input port of a phase-inverting voltage amplifier. In contrast, the differential input coupled to the common-bias circuit has a small amount of input impedance from the Miller Effect. This results in a mismatch of input impedance at the differential input pairs that can create a substantial distortion effect at the output of the amplifier. When the differential amplifier is used in a receiver, the distortion becomes more pronounced in high-speed communications because of the long distance from the signal source, the high frequency of digital communications, and the low voltage operation. The resulting distortion from the mismatch of input impedance between the differential inputs has a substantial negative effect on the receiver performance. Consequently, there is a need for a communications amplifier-receiver that reduces signal distortion induced by mismatched differential input impedance seen in common-mode differential amplifier-receivers.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment, a differential receiver-amplifier having reduced input distortion is provided. The differential receiver-amplifier receives differential data signals at differential terminals, and includes a differential signal detector having a first input terminal and a second input terminal, wherein an output signal is produced on an output terminal when a differential signal is detected on the first and second input terminals, a first differential amplifier having an output terminal coupled to the first input terminal, the first differential amplifier comprising a first differential input terminal and a second differential input terminal, wherein an input impedance at the first differential input terminal of the first differential amplifier is substantially different than an input impedance of the second differential input terminal of the first differential amplifier at an input frequency of interest, and a second differential amplifier having an output terminal coupled to the second input terminal, the second differential amplifier comprising a first differential input terminal and a second differential input terminal, wherein an input impedance at the first differential input terminal of the second differential amplifier is substantially different than an input impedance of the second differential input terminal of the second differential amplifier at an input frequency of interest, wherein, the first differential input terminal of the first differential amplifier and the second differential input terminal of the second differential amplifier are coupled to the differential positive terminal, and the second differential input terminal of the first differential amplifier and the first differential input terminal of the second differential amplifier are coupled to the differential negative terminal, wherein the resulting input impedance at the differential positive terminal is substantially equal to the resulting input impedance at the differential negative terminal.


REFERENCES:
patent: 4958133 (1990-09-01), Bazes
patent: 5323120 (1994-06-01), Ryat
patent: 5714906 (1998-02-01), Motamed et al.

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