CMOS digital level shifter circuit

Details CMOS digital level shifter circuit CMOS digital level shifter circuit

1989-07-19

1990-12-18

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307482, 3072721, 3072722, H03K 19094, H03K 190175, H03K 3284

Patent

active

049788701

ABSTRACT:
The apparatus of the present invention is a CMOS digital level shifter circuit which includes an inverter connected to a voltage generator. The voltage generator comprises an NMOS source follower connected to a directional switching element and a voltage regulating capacitor. The level shifter further includes a latch energized by the same voltage supply energizing the voltage generator. Each branch of the latch has a complementary MOS transistor pair with common gates connected to the output of the inverter and to the input signal respectively. Each complementary transistor pair is connected to the voltage supply by a latch transistor whose gate is cross-connected to the complementary transistor pair of the other branch. Whenever the one transistor in each complementary pair which is connected to ground is on, the latch transistor is latched off by the complementary transistor pair in the other branch after each voltage transition by the input signal, thereby reducing or eliminating DC power consumption, while requiring only a single voltage supply.

REFERENCES:
patent: 4786830 (1988-11-01), Foss
patent: 4801826 (1989-01-01), Cornelissen

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