Cmos digital-controlled delay gate

Details Cmos digital-controlled delay gate Cmos digital-controlled delay gate

1992-01-02

1993-07-13

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307594, 307602, H03K 1994, H03K 1920

Patent

active

052276791

ABSTRACT:
A CMOS digital-controlled delay gate is provided in which the propagation delay time can be precisely controlled by digital select control signals. The delay gate includes an inverter circuit section (12) formed of a plurality of CMOS inverters (12a-12n) each inverter having a P-channel transistor and an N-channel transistor and a control logic section (14, 16) which is responsive to the digital select control signals for changing the ratio of the total P-channel transistor size to the total N-channel transistor size in the enabled transistors. The input threshold voltage of the inverter circuit section is selectively changeable so as to produce a controllable propagation delay.

REFERENCES:
patent: 4593203 (1986-06-01), Iwahashi
patent: 4719369 (1988-01-01), Asano et al.
patent: 4806804 (1989-02-01), O'Leary
patent: 4899071 (1990-02-01), Morales
patent: 5012141 (1990-02-01), Tomisawa
patent: 5118971 (1992-06-01), Schenck

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