CMOS digital circuits with resistive shunt feedback amplifier

Details CMOS digital circuits with resistive shunt feedback amplifier CMOS digital circuits with resistive shunt feedback amplifier

1974-12-20

1976-10-12

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307215, 307216, 307218, 307304, 330 35, H03K 1908, H03K 1932, H03K 1934, H03K 1936

Patent

active

039860418

ABSTRACT:
A negative shunt feedback amplifier is disclosed for connection to the output node of a complex complementary metal oxide semiconductor logic circuit to increase the performance and reduce the FET device size. A CMOS inverter is coupled to the amplifier to restore the logic levels and to form the logic output. A first embodiment of the invention uses a resistor feedback and a second embodiment of the invention uses parallel N-channel and P-channel FETs to form the feedback impedance. The circuit has application in environments where a logic function requires a large number of FET devices resulting in a large output node capacitance and, thereby slowing the logic speed, as for example in a large DOT-OR circuit or at each output of a FET memory array.

REFERENCES:
patent: 3033995 (1962-05-01), Putzrath
patent: 3252011 (1966-05-01), Zuk
patent: 3392341 (1968-07-01), Burns
patent: 3413488 (1968-11-01), Yee
patent: 3497715 (1970-02-01), Yen
patent: 3500062 (1970-03-01), Annis
patent: 3737673 (1973-06-01), Suzuki
patent: 3829710 (1974-08-01), Hirasawa et al.
patent: 3855549 (1974-12-01), Heuner et al.
patent: 3886464 (1975-05-01), Dingwall
ho et al., "Static Shift Register for FET Technology," IBM Tech. Discl. Bull.; vol. 13, No. 6, pp. 1450-1451; 11/1970.

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