CMOS differential comparator with offset voltage

Details CMOS differential comparator with offset voltage CMOS differential comparator with offset voltage

1989-09-26

1991-08-27

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307462, 307494, H03K 524

Patent

active

050435990

ABSTRACT:
A circuit configuration in complementary MOS technology includes a comparator having two input transistors forming an input differential stage, a current source supplying the input transistors, first and second load transistors being driven by the input transistors, and an output. An output driver circuit has at least one first output transistor being controlled the output of the comparator, and a second output transistor complementary to the at least one first output transistor. The input transistors have symmetrical geometries and the load transistors have asymmetrical geometries generating a given operating characteristic of the comparator. The output driver circuit is geometrically adapted to the given operating characteristic.

REFERENCES:
patent: 3943380 (1976-03-01), Morgan et al.
patent: 4047059 (1977-09-01), Rosenthal
patent: 4511810 (1985-04-01), Yukawa
patent: 4554468 (1985-11-01), Rumbaugh et al.
patent: 4598215 (1986-07-01), Schechtman et al.
patent: 4634895 (1987-01-01), Luong
patent: 4658157 (1987-04-01), McGowan
patent: 4754169 (1988-06-01), Morris
U.S. Publication IEEE Journal of Solid State Circuits, vol. SC-17, No. 6, Dec. 1982, New York, article "MOS Operational Amplifier Design --A Tutorial Overview", by Paul R. Gray et al., pp. 969-981.
U.S. Publication, SGS Power Supply Application Manual, 1985, p. 49 of Section "UC 1524A Integrated PWM Control".
German Democratic Republic Publication Radio, Fernsehen Elektronik, 27th Year, vol. 10 (1978-10) Berlin, article, "Grundschaltungen der analogen integrierten Technik", by H. E. Krobel, pp. 621-625.
U.S. Publication AMK Berlin Congress and Convention Division, ICC Berlin Continuing Engineering Education Program, Seminar 713, Jun. 9-12, 1986, Prel. Edition of "CMOS Analog IC Design and CAD Techniques", by Ph. E. Allen, GA Inst. of Technology, pp. 352-356.

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