CMOS differential amplifier

Details CMOS differential amplifier CMOS differential amplifier

2003-02-25

2004-08-17

Choe, Henry (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S255000, C327S359000

Reexamination Certificate

active

06778014

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims priority under 35 U.S.C. 119 of German Patent Application Number 10207802.5, filed Feb. 25, 2002.
FIELD OF THE INVENTION
The invention relates to an improved CMOS differential amplifier.
BACKGROUND OF THE INVENTION
A CMOS differential amplifier of the type to which the present invention relates is described in Bazes U.S. Pat. No. 4,958,133, the entirety of which is incorporated herein by reference. A further description of the same amplifier is found in Mel Bazes, “Two Novel Fully Complementary Self-Biased CMOS Differential Amplifiers,” IEEE Journal of Solid-State Circuits, Vol. 26, No. 2, February 1991, the entirety of which is also incorporated herein by reference. Such amplifier may, for example, be used as an input stage of a clock pulse distribution circuit.
The CMOS differential amplifier of Bazes is shown FIG.
1
. It is a rail-to-rail amplifier where an in-phase control between the negative and the positive operating voltages is achieved by relieving the loads of two conventional mutually complementary CMOS folded-cascode differential amplifiers connected to each other. In the Bazes arrangement, the voltages are applied to the gate connections of the cascode transistors (MP
3
, MP
5
, MN
5
, MN
3
, MP
4
, MP
6
, MN
6
, MN
4
in
FIG. 1
) using a self-biasing arrangement, wherein the voltages present at the drain connections of the second PMOS FET (MP
5
) and the first NMOS FET (MN
5
) are fed back to the gates of the eight cascode transistors MP
3
, MP
5
, MN
5
, MN
3
, MP
4
, MP
6
, MN
6
MN
4
. This serves to make the bias voltage less dependent of process changes and changes in the temperature and operating voltage.
The CMOS differential amplifier developed by Bazes has the disadvantage that it is not suited for processing very fast signals (for example, in the 1 GHz range) of the type which can be encountered, for example, in clock pulse distribution circuits using CMOS differential amplifiers in their input stages needed to satisfy present-day market requirements. This is largely due to the fact that the cascode transistors connected to the voltage potentials—that is, the first PMOS FET (MP
3
), the third PMOS FET (MP
4
), the second NMOS FET (MN
3
) and the fourth NMOS FET (MN
4
)—cannot operate in their saturation condition, but only within their resistive range. This means that these four MOS FETs must be of relatively large dimensions, using a relatively large circuit space—a further disadvantage of such conventional CMOS differential amplifiers.
SUMMARY OF THE INVENTION
The invention provides an improved CMOS differential amplifier of the type described above, whose operation is considerably faster and which, therefore, is particularly suited to applications in clock pulse distribution circuits that can process frequencies in the 1 GHz range, and which furthermore occupies a smaller circuit area, since the transistors are used in a more efficient way.
In accordance with one aspect of the invention, a CMOS differential amplifier is provided with a circuit element whose purpose is to generate at the gate connection of the second PMOS FET a voltage that is at least as much below the gate voltage of the first PMOS FET to allow this to operate within its saturation region, and to generate at the gate connection of the first NMOS FET a voltage that is at least as much above the gate voltage of the second NMOS FET to allow this to operate within its saturation region.
In a preferred embodiment, this circuit element comprises two voltage potential dividers which enable all the cascode transistors (that is, also the first PMOS FET MP
3
, the third PMOS FET MP
4
, the second NMOS FET MN
3
and the fourth NMOS FET MN
4
) to operate within their saturation region, whereby the current flow through these transistors—and therefore the switching speed of the push-pull stage of the CMOS differential amplifier—can be increased. This makes it possible to use the CMOS differential amplifier, for example, in the input stages of clock pulse distribution circuits which distribute clock signals in the 1 GHz range. Furthermore, a more favorable relation between the transistor surface area and the current that can be drawn by the transistors is achieved.
According to a further embodiment of the CMOS differential amplifier according to the invention, both the first voltage divider and the second voltage divider each contain a resistor controlled by means of the bias voltage to ensure the stabilization of even the MOS FETs (MP
3
, MP
4
, MN
3
, MN
4
) whose gate connections are no longer directly connected to the fed-back bias voltage, in the case of changes in the process conditions, the temperature or the supply voltage.


REFERENCES:
patent: 4958133 (1990-09-01), Bazes
patent: 6043708 (2000-03-01), Barr
patent: 6496066 (2002-12-01), Colonna et al.
“Robust Design of Rail-to-Rail CMOS Operational Amplifiers for a Low Power Supply Voltage,” IEEE Journal of Solid-State Circuits, vol. 31, No. 2, Feb. 1996, pp. 146-156 (Satoshi Sakurai).

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