CMOS device with high density wiring layout

Details CMOS device with high density wiring layout CMOS device with high density wiring layout

1982-03-02

1985-06-11

Edlow, Martin H.

357 71, 357 59, 357 88, H01L 2348, H01L 2904, H01L 2702

Patent

active

045232164

ABSTRACT:
A CMOS device has P- and N-channel transistors sandwiching an isolation region formed on a semiconductor substrate. The drain regions, as well as the gate regions, of both transistors are connected by respective wiring layers made of polycrystalline silicon. Electrical contacts between the drain-connecting polycrystalline silicon wiring layer and each of the drain regions have a symmetrical structure in both transistors. In the electrical contacts, impurity diffusion regions having the same conductivity type as the drain regions and being contiguous with the drain regions are formed on the semiconductor substrate and the well region under the polycrystalline silicon wiring layer. Contact holes are formed in the insulating layer on the impurity diffusion region and on the drain region, and a conductive layer lies within the contact holes to connect the impurity diffusion regions to the polycrystalline silicon wiring layer. Further, a power source line and other wiring layers are provided on an isolation region between the transistors.

REFERENCES:
patent: 3877051 (1975-04-01), Calhoun et al.
patent: 4163242 (1979-07-01), Stein
patent: 4262340 (1981-04-01), Sasaki et al.
patent: 4322736 (1982-03-01), Sasaki et al.
patent: 4348746 (1982-09-01), Okabayashi et al.
patent: 4356504 (1982-10-01), Tozun
patent: 4392150 (1983-07-01), Courreges
patent: 4412237 (1983-10-01), Matsumura et al.

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