CMOS device having Schottky diode for latch-up prevention

Details CMOS device having Schottky diode for latch-up prevention CMOS device having Schottky diode for latch-up prevention

1987-08-04

1990-05-01

Wojciechowicz, Edward J.

357 15, H01L 2702

Patent

active

049223178

ABSTRACT:
A CMOS device having an nMOS formed in a p-type substrate region, and a pMOS formed in an n-type substrate region is provided with a Schottky barrier junction for collecting holes injected into the n-type substrate region, to prevent latch-up. The Schottky barrier junction is formed by a metal electrode and the n-type substrate region, and is located between the pMOS and the nMOS.

REFERENCES:
patent: 4209713 (1980-06-01), Satou et al.
patent: 4327368 (1982-04-01), Uchida
patent: 4477310 (1984-10-01), Park et al.
patent: 4513309 (1985-04-01), Cricchi
patent: 4574467 (1986-03-01), Halfacre et al.
patent: 4593459 (1986-06-01), Poppert et al.
patent: 4646124 (1987-02-01), Zunino
patent: 4647957 (1987-03-01), Coquin et al.
patent: 4689653 (1987-08-01), Miyazaki
patent: 4760035 (1988-07-01), Pfleiderer et al.
Krick-IBM Tech. Dis. Bul.-vol. 13, No. 1, Jun. 1970.

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