CMOS device having reduced spacing between N and P channel

Details CMOS device having reduced spacing between N and P channel CMOS device having reduced spacing between N and P channel

1987-05-29

1989-05-09

James, Andrew J.

357 49, 357 86, H01L 2702

Patent

active

048293598

ABSTRACT:
The separation constraint between the respective junctions formed between the drain regions of the complementary transistors and the semiconductor material in which they are formed is obviated by a structure which permits the respective drain regions of the opposite conductivity type transistors to have a reduced (effecting to zero) mutual separation and, at the same time, prevent the depletion regions fomed between the junctions defined by these source regions and the semiconductor material in which they are formed from spreading into contact with one another and thereby shorting the transistors together. This objective is achieved by a structure in which the source regions of the respective P and N channel transistors are formed so as to directly abut against one another and to be contiguous with a layer of buried dielectric isolation therebeneath. The buried dielectric layer extends from the bottom portions of the drain regions to a prescribed depth in each of the P-well region and the N-type substrate, so as to effectively provide a barrier between depletion region associated with the junction defined by the P well and N substrate the depletion regions formed between the N+ drain region and the P-well and the P+ drain region and the N-type substrate.

REFERENCES:
patent: 4399605 (1983-08-01), Dash et al.
patent: 4507846 (1985-04-01), Ohno
patent: 4633289 (1986-12-01), Chen
patent: 4677735 (1987-07-01), Malhi
patent: 4778775 (1988-10-01), Tzeng

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