CMOS device having high-density resistance elements

Details CMOS device having high-density resistance elements CMOS device having high-density resistance elements

1999-05-19

2004-05-11

Eckert, George (Department: 2815)

Semiconductor device manufacturing: process

Making passive device

Resistor

C438S381000, C438S383000, C438S384000, C438S385000, C257S528000, C257S379000, C257S536000, C257S537000, C257S538000, C257S516000, C257S218000, C257S904000

Reexamination Certificate

active

06734075

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of Invention
The present invention relates to a CMOS device in which a p-channel MOS transistor and an n-channel MOS transistor are formed on the same semiconductor substrate. More particularly, the present invention relates to a CMOS device in which a resistance element is formed utilizing a channel stopper and well.
2. Related Art
FIG. 5
is a cross-sectional view showing a common element structure of p-well type CMOS device. A semiconductor substrate
1
or silicon (Si) used in this structure is of n-type, and p-type well
2
is deeply formed on a surface of the semiconductor substrate
1
. MOS transistor
3
of p-channel is formed on a surface of n-type semiconductor substrate
1
, which MOS transistor
3
of p-channel is referred to as P-MOS in this specification, hereinafter, and MOS transistor
4
of n-channel is formed on a surface of p-type well
2
, which MOS transistor
4
of n-channel is referred to as N-MOS in this specification, hereinafter. On a surface of the semiconductor substrate
1
, p
+
-type regions
5
A and
5
B, which become a source/drain of P-MOS
3
, are shallowly formed. In the same manner, on a surface of the well
2
, n
+
-type regions
6
A and
6
B, which become a source/drain of N-MOS
4
, are shallowly formed. In order to separate P-MOS
3
and N-MOS
4
from each other, n-type channel stopper
7
is formed on the side of P-MOS
3
on a surface of the semiconductor substrate
1
, and also p-type channel stopper
8
is formed on the side of N-MOS
4
on a surface of the well
2
.
Except for an element region, a surface of the semiconductor substrate
1
having the above inner structure is covered with a thick field oxide film (SiO
2
)
9
. On the other hand, a surface of the element region is covered with a thin gate oxide film (SiO
2
)
10
. On the gate oxide film
10
, a polycrystal silicon layer
11
, which becomes a gate electrode, is formed. As a passivation film covering an overall surface of the device, for example, BPSG (borophospho silicate glass) film
12
is laminated. On an upper surface of this BPSG film
12
, metallic wiring layers
13
A,
13
B,
13
c
made of metal such as Al (aluminum) are laminated. The metallic wiring layers
13
A,
13
B,
13
C are respectively connected with source drain regions
5
A,
5
B,
6
A,
6
B, and gate electrodes
11
via contact windows formed on BPSG film
12
and also formed in portions of a thermal oxidation film formed below BPSG film
12
.
When a resistance element necessary for the circuit structure is incorporated into a CMOS device having the above structure, it is conventional to form a resistance element by various methods shown in
FIGS. 6
to
9
. For example, in the example shown in
FIG. 6
, a polycrystal silicon layer
11
R is formed on a thick field oxide film
9
in a portion except for the element region of CMOS shown in FIG.
5
. Both end portions of the polycrystal silicon layer
11
R, which is used as a resistance element, are connected with metallic layers
13
D,
13
D′ used for connection.
On the other hand, in the example shown in
FIG. 7
, a source/drain region in the element region of CMOS is extended so that it can be used as a resistance element. That is, p-type region
5
R on the side of P-MOS is not separated for the source and drain, but it is formed as one continuous resistance region, and both end portions of it are connected with the metallic layers
13
D,
13
D′. In this element region, the polycrystal silicon film
11
for the use of gate electrode shown in
FIG. 5
is not formed. In the same manner, when a resistance element is formed on the side of N-MOS, n-type region
6
R is not separated as a source and drain, but it is formed as one continuous resistance region. Both end portions of this n-type resistance region
6
R are connected with the metallic layers
13
E.
13
E′ used for connection. Also in this case, the transistor is not operated as N-MOS. Therefore, the polycrystal silicon film
11
used for the gate electrode is not formed on the gate oxide film
10
.
FIG. 8
is a view showing an example in which p-type well
2
R formed as an element region of N-MOS is used as a resistance element. In both end portions of this p-type well
2
R, p
+
-type regions
5
A,
5
B utilized as a source/drain region of P-MOS are formed instead of n-type source/drain regions
6
A,
6
B shown in
FIG. 5
, and these are connected with the metallic layers
13
D,
13
D′ used for connection. Also in this case, the transistor is not operated as N-MOS. Therefore, the polycrystal silicon film
11
used for the gate electrode is not formed on the gate oxide film
10
.
FIG. 9
is a view showing an example in which an exclusive resistance element is formed in the element region of CMOS. That is, an exclusive p-type region
14
R is formed between p-type source/drain regions
5
A,
5
B in the element region on the side of P-MOS so that they can be connected with each other, and the thus formed exclusive p-type region
14
R is used as a resistance element. Both end portions of this resistance region
14
R are connected with the metallic layers
13
D,
13
D′ via p-type regions
5
A,
5
B. Also in this case, the transistor is not operated as P-MOS. Therefore, the polycrystal silicon film
11
used for the gate electrode is not formed on the gate oxide film
10
. When an exclusive resistance element is formed in the element region on the side of N-MOS, an exclusive n-type region
15
R is formed on a surface of p-type well
2
. Both end portions of this n-type resistance region
15
R are connected with the metallic layers
13
E,
13
E′ via n-type source/drain regions
6
A,
6
B. Also in this case, the transistor is not operated as N-MOS. Therefore, the polycrystal silicon film
11
used for the gate electrode is not formed on the gate oxide film
10
.
In the conventional methods shown in
FIGS. 6
to
9
, it is intended that all resistance elements are arranged on a plane of the semiconductor substrate. Therefore, the conventional methods are not suitable for increasing the density of arrangement of components. For example, it is considered that a resistance element of two-layer structure can be formed when the resistance element
11
R, which is arranged on the substrate, composed of a polycrystal silicon layer shown in
FIG. 6
is combined with one of the resistance elements
5
R,
6
R,
2
R,
14
R,
15
R, which are arranged in the substrate, shown in
FIGS. 7
to
9
, so that it becomes possible to increase the density of arrangement of components. However, from an actual viewpoint, the resistance elements arranged in the substrate are formed on the lower side of the thin gate oxide film
10
. Therefore, even if the polycrystal silicon layer
11
used for the gate electrode is formed on an upper side of this gate oxide film
10
, it is difficult for the polycrystal silicon layer
11
to become a second resistance element which is electrically separated from the resistance element arranged in the substrate. This is a problem to be solved by the present invention.
SUMMARY OF INVENTION
It is an object of the present invention to provide a CMOS device in which: a plurality of resistance elements are formed at high density when resistance elements of a two-layer structure are formed, with the resistance elements being divided into an inside and an upper layer of a semiconductor substrate underneath thick field oxide film
9
high resistance elements easily formed without changing the forming process.
The above objects of the present invention can be accomplished by a CMOS device in which: a second electric conduction type well is formed on a first conduction type semiconductor substrate; a first MOS transistor of a reverse electric conduction type channel is formed on a surface of the semiconductor substrate; a second MOS transistor of first conduction type channel is formed on a surface of the well; and a resistance element is formed in the semiconductor substrate on a lower side of a thick field oxide film cove

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