Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1999-06-22
2001-08-14
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S307000
Reexamination Certificate
active
06275094
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor devices and circuits and methods of operation. More particularly, the invention relates to apparatus and methods for dynamic control and adjustment of threshold voltage in CMOS devices and circuits.
2. Description of Prior Art
The variation in threshold voltage of Field Effect Transistors (FET) leads to undesirable effects and limitations in the operating range of integrated circuits. Many analog circuits depend on the use of differential pairs of transistors and the threshold matching inherent to those circuits. Modern CMOS technology, while well controlled, can exhibit device threshold voltage (Vth) mismatches in the multi-millivolt range and this can be too much for certain types of circuits to achieve aggressive specifications. Analog to digital converters of the flash type, comparators, and certain types of amplifiers are susceptible to threshold mismatches. Altering the threshold voltage (Vth) of FETs by circuit means has been used in the past to compensate for uncertainty in the manufacturing process. Typically, a charge pump or other voltage adjustment means is used to change the bias on the substrate or back gate of the FET to alter the threshold voltage of the FETs. However, compensation was done to all of a particular type in an integrated circuit as a whole, because the substrate of at least one of the device types—P or N—was a common element in the physical structure.
With the advent of Silicon-On-Insulator (SOI) technology, the back gates of both device types—P and N—are now isolated for each individual transistor. Prior art has taught the use of driving isolated back gates to either a high reverse bias of the source-substrate junction to minimize source-drain leakage current in the “off” mode, and to a slightly forward biased region of operation to enhance the source-drain current in the “on” mode. What is needed in the art is an apparatus and method of adjusting the threshold voltage of an individual CMOS transistor in a dynamic mode, so that the transistor can either attain and maintain a characteristic that matches another transistor in the circuit, or such that the characteristics of the circuit can be changed by altering the threshold voltage of an individual transistor.
Prior art related to threshold control includes the following:
U.S. Pat. No. 5,557,234 entitled “Differential Amplifier with Mismatch Correction Using Floating Gates”, issued to S. Collins on Sep. 17, 1996 (Collins) discloses a differential amplifier that is adjustable to counteract mismatch without introducing circuit asymmetry. In one embodiment one of the input transistors floating gates is charged to reduce amplifier offset voltage extrapolated to zero input transistor drain current. The amplifier then adjusts to reduce discrepancy between actual design values of input transistor drain voltage by charging one or both of the drain load transistor floating gates. The amplifier may be arranged as an operational amplifier with a second state connected to an input transistor drain. The operational amplifier input offset voltage is determined by the second stage output with a reference and feeding a resulting differences signal to the amplifier input. The input offset voltage is counterbalanced by charging an input transistor floating gate to reduce the difference signal.
U.S. Pat. No. 5,838,047 entitled “CMOS Substrate Biasing for Threshold Voltage Control” to T. Yamauchi et al., issued Nov. 17, 1998 (Yamauchi) discloses a CMOS device in which a potential of Bcc level is applied to the substrate of the P device and a potential Vs. is applied to the substrate of the N device in a standby state. As such, the voltage between the source and substrate of the P and N transistors becomes 0 V. In an active state, potentials render the voltage between the source and substrate lower than the built in potentials are applied to respective substrates of the P and N devices. As such, the threshold voltage of the transistor is lowered in an active state compared to a standby state, and almost no leakage current flows between the source and substrate.
IBM Technical Disclosure Bulletin Vol. 25, No. 11A, April 1983, pp. 5829-30, by D. E. DeBar entitled “Dynamic Substrate Bias to Achieve Radiation Hardening” (DeBar) discloses a substrate bias compensation which monitors the threshold voltage of a sample FET circuit on an integrated circuit chip. The circuit modifies the substrate voltage for the chip to compensate for variations in the monitor threshold voltage due to radiation damage such as might occur in a space satellite exposed to a solar flare. A voltage divider establishes a voltage reference for operational amplifier. The amplifier will force the substrate of a FET to whatever is needed to ensure that the load voltage equals the reference voltage. When gamma rays pass through the FET, the intrinsic threshold voltage of the transistor will lower. The V
t
is held fixed by the voltage divider and the transistor will tend to conduct more heavily, which will in turn, tend to lower the reference voltage. The reference voltage is fed back to a non-inverting input of the amplifier. The output of the amplifier will move more negative to a voltage such that the load voltage will equal the reference voltage and the intrinsic threshold voltage equals the threshold for the drain current.
Japanese patent 9-162417 assigned to Northern Telecom, Ltd., issued Jun. 20, 1997 (Northern) discloses a silicon on insulator substrate containing an N and P devices formed in selected areas of the insulation dielectric layer. A pair of back gate electrodes is formed in the silicon substrate under the insulation dielectric layer. The first back gate electrode is extended to the downside of the P device. The second back gate electrode is extended to the downside of the N device. Each back gate electrode is a contact part, through which bias voltage is applied to the devices. The threshold potential of the devices is controlled by regulating the bias voltage applied to the back gate electrodes.
Japanese patent 3-66159 to K. Hiroyuki et al., issued Mar. 20, 1991 (Hiroyuki) discloses a back gate potential impressed by an interlayer connection formed under a P type silicon on insulator layer via resistance element formed so as to be connected to the inner layer. A back gate voltage input terminal is formed at the resistance element. A seed which transforms a polycrystalline layer into a single crystal may be used as the interlayer interconnection layer. A layer in which a CMOS inverter is formed and the resistance element used to adjust a threshold voltage of the CMOS inverter are formed in different layers. Consequently, the CMOS inverter and the resistance element for back gate voltage adjustment use are not formed on the same plane. As a result, the CMOS inverter can be integrated highly.
U.S. Pat. No. 5,814,899 entitled “SOI-Type Semiconductor Device with Variable Threshold Voltages” to K. Okumura et al., issued Sep. 29, 1998 (Okumura) discloses in an SOI type device, a power supply voltage applied to back gates of P-channel devices in a standby mode, and a voltage lower than the power supply voltage is applied to the back gates of the P-channel devices in an active mode. A ground voltage is applied to the back gates of the N-channel devices in the standby mode, and a voltage higher than the ground voltage is applied to the back gates of the N-channel device sin an active mode. Since the transistors are electrically isolated from the substrate, no short circuit is generated between the transistor wells and the substrate. Also, no substantial parasitic capacitance exists between the transistor well and the substrate, a transition time from standby mode to an active mode or vice-a-versa can be reduced.
U.S. Pat. No. 5,646,900 entitled “Sense Amplifier Including MOS Transistors Having Threshold Voltages Controlled Dynamically in a Semiconductor Memory Device” to M. Tsukude et al., issued Jul. 8, 1997 (Tsukude) discloses an N-channel sense am
Cranford, Jr. Hayden Clavie
Stephens Geoffrey B.
Cockburn Joscelyn G.
Cunningham Terry D.
International Business Machines - Corporation
Redmond, Jr. Joseph C.
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