CMOS .DELTA.V.sub.BE bias current generator

Details CMOS .DELTA.V.sub.BE bias current generator CMOS .DELTA.V.sub.BE bias current generator

1985-08-22

1986-10-21

Salce, Patrick R.

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

323312, 307297, G05F 316

Patent

active

046188169

ABSTRACT:
In a CMOS structure a pair of BJTs are provided with lateral collectors and operated at different current densities. The lateral collectors are coupled to a current mirror load which provides a single ended output node. The pair bases are coupled together and to the current mirror load input so that the lateral BJT collectors operate at low potential. A current source supplies tail current and a resistor is coupled in series with the low current density BJT. The single ended output node is coupled to a current mirror that determines the BJT tail current. The circuit therefore has a negative feedback loop around the BJTs that will stabilize operation so that .DELTA.V.sub.BE appears across the resistor. The resistor can be chosen so that the overall circuit temperature coefficient can be established at a desired value.

REFERENCES:
patent: 4147944 (1979-04-01), Monticelli
patent: 4176308 (1979-11-01), Dobkin et al.
patent: 4319181 (1982-03-01), Wrathall
patent: 4563632 (1986-01-01), Palara et al.

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